def test_ram_banks(self):
sim = Simulator(self.mbc)
def proc():
yield from self.reset()
yield from self.write(0x4000, 0x1F)
assert (yield self.mbc.ram_bank) == 0xF
yield from self.write(0x4000, 0x7A)
assert (yield self.mbc.ram_bank) == 0xA
sim.add_process(proc)
sim.reset()
sim.run()
def test_ram_en(self):
sim = Simulator(self.mbc)
def proc():
yield from self.reset()
assert (yield self.mbc.ram_en) == 0
yield from self.write(0x0000, 0x0A)
assert (yield self.mbc.ram_en) == 1
yield from self.write(0x0000, 0x1A)
assert (yield self.mbc.ram_en) == 0
sim.add_process(proc)
sim.reset()
sim.run()
def test_rom_banks(self):
sim = Simulator(self.mbc)
def proc():
yield from self.reset()
yield from self.assert_rom_banks(0x000, 0x001)
yield from self.write(0x2000, 0x42)
yield from self.assert_rom_banks(0x000, 0x042)
yield from self.write(0x3000, 0x01)
yield from self.assert_rom_banks(0x000, 0x142)
yield from self.write(0x2000, 0x00)
yield from self.assert_rom_banks(0x000, 0x100)
yield from self.write(0x3000, 0x00)
yield from self.assert_rom_banks(0x000, 0x000)
sim.add_process(proc)
sim.reset()
sim.run()
yield from jtagPDI((0x4C, 1), (0xEB, 1))
yield
yield from jtagPDI((0xCA, 0), (0xEB, 1))
yield
yield from jtagPDI((0x01, 1), (0xEB, 1))
yield
yield from jtagPDI((0x00, 0), (0xEB, 1))
yield
yield from jtagPDI((0x01, 1), (0xEB, 1))
yield
yield from jtagPDI((0x00, 0), (0xEB, 1))
yield
yield
yield
yield
sim = Simulator(subtarget)
# Define the JTAG clock to have a period of 1/4MHz
#sim.add_clock(250e-9, domain = 'jtag')
sim.add_clock(2e-6, domain='jtag')
# Define the system clock to have a period of 1/48MHz
sim.add_clock(20.8e-9)
sim.add_sync_process(benchSync, domain='sync')
sim.add_sync_process(benchJTAG, domain='jtag')
with sim.write_vcd('jtag_pdi-sniffer.vcd'):
sim.reset()
sim.run()