def test_add_symmetry_const():
name = f'ckt_{get_test_id()}'
netlist = ota_six(name)
constraints = [
{"constraint": "IsDigital", "isTrue": True}
]
example = build_example(name, netlist, constraints)
ckt_library = compiler_input(example, name, pdk_path, config_path)
ckt = ckt_library.find(name)
with set_context(ckt.constraints):
x = constraint.SymmetricBlocks(direction="V", pairs=[["MN4", "MN3"]])
const_pairs = {"MN4": "MN3"} # skip dictionary element
with pytest.raises(KeyError):
add_or_revert_const(const_pairs, ckt.constraints, list())
assert len(ckt.constraints) == 1
const_pairs = [["MN4", "MN3"]]
add_or_revert_const(const_pairs, ckt.constraints, list())
assert len(ckt.constraints) == 2
assert ckt.constraints[1] == x
const_pairs = [["MN4", "MN5"]] # Skip unequal size
add_or_revert_const(const_pairs, ckt.constraints, list())
assert len(ckt.constraints) == 2
const_pairs = [["VIN", "VIP"]] # Skip net
add_or_revert_const(const_pairs, ckt.constraints, list())
assert len(ckt.constraints) == 2
clean_data(name)
def test_symm_net():
name = f'ckt_{get_test_id()}'
netlist = ota_six(name)
constraints = [
{"constraint": "IsDigital", "isTrue": True}
]
example = build_example(name, netlist, constraints)
ckt_library = compiler_input(example, name, pdk_path, config_path)
ckt = ckt_library.find(name)
G = Graph(ckt)
pairs, pinsA, pinsB = symmnet_device_pairs(G, 'VIN', 'VIP', list(), None, True)
assert pairs == {'VIN': 'VIP', 'MN4': 'MN3'}
assert pinsA == ['MN4/G', 'VIN']
assert pinsB == ['MN3/G', 'VIP']
pairs, pinsA, pinsB = symmnet_device_pairs(G, 'VIN', 'VIP', [{'MN3', 'MN4'}], None)
assert pairs == {'VIN': 'VIP', 'MN4': 'MN3'}
pairs, pinsA, pinsB = symmnet_device_pairs(G, 'VIN', 'VIP', ['MN3'], None)
assert pairs is None
pairs, pinsA, pinsB = symmnet_device_pairs(G, "VIN", "VIP", ["MN4"], None)
assert pairs is None
pairs, pinsA, pinsB = symmnet_device_pairs(G, "VIN", "VIP", list(), ["MN4"])
assert pairs is None
pairs, pinsA, pinsB = symmnet_device_pairs(G, "VIN", "VIP", list(), ["MN3"])
assert pairs is None
pairs, pinsA, pinsB = symmnet_device_pairs(G, "IBIAS", "TAIL", list(), ["MN3"])
assert pairs is None
pairs, pinsA, pinsB = symmnet_device_pairs(G, "VON", "VOP", list(), ["MN3"])
assert pairs is None
pairs, pinsA, pinsB = symmnet_device_pairs(G, "VIN", "VON", list(), ["MN3"])
assert pairs is None
clean_data(name)
def test_merge_parallel():
# TODO Do not identify array when setup set as false
name = f'ckt_{get_test_id()}'.upper()
netlist = ota_six(name)
constraints = [{
"constraint": "PowerPorts",
"ports": ["VCCX"]
}, {
"constraint": "GroundPorts",
"ports": ["VSSX"]
}, {
"constraint": "MergeParallelDevices",
"isTrue": False
}]
example = build_example(name, netlist, constraints)
generate_hierarchy(example, name, out_path, False, pdk_path, False)
clean_data(name)
pass
def test_dont_constrain_clk():
# TODO Do not constrain clock connected devices
name = f'ckt_{get_test_id()}'.upper()
netlist = ota_six(name)
constraints = [{
"constraint": "PowerPorts",
"ports": ["VCCX"]
}, {
"constraint": "GroundPorts",
"ports": ["VSSX"]
}, {
"constraint": "ClockPorts",
"ports": ["vin"]
}]
example = build_example(name, netlist, constraints)
generate_hierarchy(example, name, out_path, False, pdk_path, False)
clean_data(name)
pass
def test_ota_six():
name = f'ckt_{get_test_id()}'.upper()
netlist = ota_six(name)
constraints = [{
"constraint": "PowerPorts",
"ports": ["VCCX"]
}, {
"constraint": "GroundPorts",
"ports": ["VSSX"]
}]
example = build_example(name, netlist, constraints)
ckt_library = compiler_input(example, name, pdk_path, config_path)
all_modules = set([name, "SCM_NMOS", "SCM_PMOS", "DP_NMOS_B"])
available_modules = set([
module.name for module in ckt_library
if isinstance(module, SubCircuit)
])
assert available_modules == all_modules, f"{available_modules}"
clean_data(name)
def test_dont_const():
name = f'ckt_{get_test_id()}'.upper()
netlist = ota_six(name)
constraints = [{
"constraint": "PowerPorts",
"ports": ["VCCX"]
}, {
"constraint": "GroundPorts",
"ports": ["VSSX"]
}, {
"constraint": "AutoConstraint",
"isTrue": False
}]
example = build_example(name, netlist, constraints)
generate_hierarchy(example, name, out_path, False, pdk_path, False)
gen_const_path = out_path / f'{name}.verilog.json'
with open(gen_const_path, "r") as fp:
gen_const = next(x for x in json.load(fp)['modules']
if x['name'] == name)["constraints"]
assert len(gen_const) == 3, f"{gen_const}"
clean_data(name)