#! /usr/bin/env python import uvmf_gen ## The input to this call is the name of the desired interface intf = uvmf_gen.InterfaceClass('def') ## Specify the clock and reset signal for the interface intf.clock = 'pdClk' intf.reset = 'pdRst' ## Specify the ports associated with this interface. ## addPort(<name>,<width>,[input|output|inout]) intf.addPort('def_wdata', 8, 'input') intf.addPort('def_addr', 16, 'input') intf.addPort('def_rdata', 8, 'output') ## Specify transaction variables for the interface. ## addTransVar(<name>,<type>) ## optionally can specify if this variable may be specified as 'rand' intf.addTransVar('def_trnVar1', 'byte', isrand=False) intf.addTransVar('def_trnVar2', 'int', isrand=True) intf.addTransVar('def_trnVar3', 'bit [15:0]', isrand=False) ## Specify configuration variables for the interface. ## addConfigVar(<name>,<type>) ## optionally can specify if this variable may be specified as 'rand' intf.addConfigVar('def_cfgVar1', 'bit', isrand=False) intf.addConfigVar('def_cfgVar2', 'int', isrand=True) intf.addConfigVar('def_cfgVar3', 'bit [3:0]', isrand=False)
#! /usr/bin/env python import uvmf_gen ## The input to this call is the name of the desired interface intf = uvmf_gen.InterfaceClass('decode_out') ## Specify parameters for this interface package. ## These parameters can be used when defining signal and variable sizes. # addHdlParamDef(<name>,<type>,<value>) ## Specify the clock and reset signal for the interface intf.clock = 'clock' intf.reset = 'reset' intf.resetAssertionLevel = True ## Specify the ports associated with this interface. ## The direction is from the perspective of the test bench as an INITIATOR on the bus. ## addPort(<name>,<width>,[input|output|inout]) intf.addPort('E_Control',6,'input') intf.addPort('Mem_Control',1,'input') intf.addPort('W_Control',2,'input') intf.addPort('IR',16,'input') intf.addPort('npc_out',16,'input') ## Specify typedef for inclusion in typedefs_hdl file # addHdlTypedef(<name>,<type>) #intf.addHdlTypedef('op_t','enum bit [3:0] { ADD=4\'b0001 , AND=4\'b0101 , NOT=4\'b1001 , LD=4\'b0010 , LDR=4\'b0110 , LDI=4\'b1010 , LEA=4\'b1110 , ST=4\'b0011 , STR=4\'b0111 , STI=4\'b1011 }') #intf.addHdlTypedef('reg_t','enum bit [2:0] { R0=3\'b000 , R1=3\'b001 , R2=3\'b010 , R3=3\'b011 , R4=3\'b100 , R5=3\'b101 , R6=3\'b110 , R7=3\'b111 }') #intf.addHdlTypedef('imm5_t','bit [4:0]') #intf.addHdlTypedef('immediate_t','bit')
#! /usr/bin/env python import uvmf_gen ## The input to this call is the name of the desired interface intf = uvmf_gen.InterfaceClass('decode_in') ## Specify parameters for this interface package. ## These parameters can be used when defining signal and variable sizes. # addHdlParamDef(<name>,<type>,<value>) ## Specify the clock and reset signal for the interface intf.clock = 'clock' intf.reset = 'reset' intf.resetAssertionLevel = True ## Specify the ports associated with this interface. ## The direction is from the perspective of the test bench as an INITIATOR on the bus. ## addPort(<name>,<width>,[input|output|inout]) intf.addPort('enable_decode', 1, 'output') intf.addPort('dout', 16, 'output') intf.addPort('npc_in', 16, 'output') ## Specify typedef for inclusion in typedefs_hdl file # addHdlTypedef(<name>,<type>) intf.addHdlTypedef( 'op_t', 'enum bit [3:0] { ADD=4\'b0001 , AND=4\'b0101 , NOT=4\'b1001 , LD=4\'b0010 , LDR=4\'b0110 , LDI=4\'b1010 , LEA=4\'b1110 , ST=4\'b0011 , STR=4\'b0111 , STI=4\'b1011 , BR=4\'0000, JMP=4\'1100}' ) intf.addHdlTypedef( 'reg_t',
#! /usr/bin/env python import uvmf_gen ## The input to this call is the name of the desired interface intf = uvmf_gen.InterfaceClass('ghi') ## Specify the clock and reset signal for the interface intf.clock = 'pgClk' intf.reset = 'pgRst' ## Specify the ports associated with this interface. ## addPort(<name>,<width>,[input|output|inout]) intf.addPort('ghi_wdata', 8, 'input') intf.addPort('ghi_addr', 16, 'input') intf.addPort('ghi_rdata', 8, 'output') ## Specify transaction variables for the interface. ## addTransVar(<name>,<type>) ## optionally can specify if this variable may be specified as 'rand' intf.addTransVar('ghi_trnVar1', 'byte', isrand=False) intf.addTransVar('ghi_trnVar2', 'int', isrand=True) intf.addTransVar('ghi_trnVar3', 'bit [15:0]', isrand=False) ## Specify configuration variables for the interface. ## addConfigVar(<name>,<type>) ## optionally can specify if this variable may be specified as 'rand' intf.addConfigVar('ghi_cfgVar1', 'bit', isrand=False) intf.addConfigVar('ghi_cfgVar2', 'int', isrand=True) intf.addConfigVar('ghi_cfgVar3', 'bit [3:0]', isrand=False)
#! /usr/bin/env python import uvmf_gen ## The input to this call is the name of the desired interface intf = uvmf_gen.InterfaceClass('jkl') ## Specify the clock and reset signal for the interface intf.clock = 'pjClk' intf.reset = 'pjRst' ## Specify the ports associated with this interface. ## addPort(<name>,<width>,[input|output|inout]) intf.addPort('jkl_wdata', 8, 'input') intf.addPort('jkl_addr', 16, 'input') intf.addPort('jkl_rdata', 8, 'output') ## Specify transaction variables for the interface. ## addTransVar(<name>,<type>) ## optionally can specify if this variable may be specified as 'rand' intf.addTransVar('jkl_trnVar1', 'byte', isrand=False) intf.addTransVar('jkl_trnVar2', 'int', isrand=True) intf.addTransVar('jkl_trnVar3', 'bit [15:0]', isrand=False) ## Specify configuration variables for the interface. ## addConfigVar(<name>,<type>) ## optionally can specify if this variable may be specified as 'rand' intf.addConfigVar('jkl_cfgVar1', 'bit', isrand=False) intf.addConfigVar('jkl_cfgVar2', 'int', isrand=True) intf.addConfigVar('jkl_cfgVar3', 'bit [3:0]', isrand=False)
## This example will produce several new interface/agent packages, an ## environment package and a project bench. Note that the ## 'def','ghi' and 'jkl' interfaces are simply copies of the ## first agent and are NOT examples of what you should actually ## be doing. They are included here to fill out the contents of ## the environment example. ## ## It is allowable to split the creation of interfaces, environments ## and benches into separate config files to be executed ## independently of one another, just make sure that the uvmf_gen ## module is imported at the top of each file. import uvmf_gen ## The input to this call is the name of the desired interface intf = uvmf_gen.InterfaceClass('abc') ## Specify the clock and reset signal for the interface intf.clock = 'paClk' intf.reset = 'paRst' ## Specify the ports associated with this interface. ## addPort(<name>,<width>,[input|output|inout]) intf.addPort('wdata', 8, 'input') intf.addPort('addr', 16, 'input') intf.addPort('rdata', 8, 'output') intf.addHdlParamDef('NUM_FILTERS', 'int', '20') intf.addHdlParamDef('NUM_TAPS', 'int', '12') ## Specify transaction variables for the interface.