def get_inv_err_f_j_bdds():
assert spec.num_justice <= 1
assert spec.num_fairness <= 1
j_bdd = get_bdd_for_value(aiglib.get_justice_lit(spec, 0, 0)) \
if spec.num_justice == 1 \
else cudd.One()
f_bdd = get_bdd_for_value(aiglib.get_aiger_symbol(spec.fairness, 0).lit) \
if spec.num_fairness == 1 \
else cudd.One()
inv_bdd = cudd.One()
if spec.num_constraints > 0:
for i in range(spec.num_constraints):
bdd = get_bdd_for_value(aiglib.get_aiger_symbol(spec.constraints, i).lit)
inv_bdd = inv_bdd & bdd
err_bdd = cudd.Zero()
if spec.num_bad > 0:
for i in range(spec.num_bad):
bdd = get_bdd_for_value(aiglib.get_aiger_symbol(spec.bad, i).lit)
err_bdd = err_bdd | bdd
elif spec.num_outputs == 1:
err_bdd = get_bdd_for_value(aiglib.get_aiger_symbol(spec.outputs, 0).lit)
return inv_bdd, err_bdd, f_bdd, j_bdd
def get_new_s_lit(old_lit):
""" :return: _signed_ literal """
# 2 is the input of a counter aig
# 2 -> spec.justice[0].lits[0], 3 -> negate(spec.fairness.lit)
# counter_other_lit -> counter_other_lit + shift
if strip_lit(old_lit) == reset:
res = aiglib.get_justice_lit(spec, 0, 0)
if is_negated(old_lit):
res = negate(res)
return res
if strip_lit(old_lit) == inc:
if not spec.num_fairness:
# Here we have something like GF true -> GF just
# so we always increment our counter
if is_negated(old_lit):
return 0
return 1
# here we have GF fair -> GF just
res = aiglib.get_ith_fairness(spec, 0).lit
if is_negated(old_lit):
res = negate(res)
return res
return old_lit + shift
def get_new_s_lit(old_lit):
""" :return: _signed_ literal """
# 2 is the input of a counter aig
# 2 -> spec.justice[0].lits[0], 3 -> negate(spec.fairness.lit)
# counter_other_lit -> counter_other_lit + shift
if strip_lit(old_lit) == reset:
res = aiglib.get_justice_lit(spec, 0, 0)
if is_negated(old_lit):
res = negate(res)
return res
if strip_lit(old_lit) == inc:
if not spec.num_fairness:
# Here we have something like GF true -> GF just
# so we always increment our counter
if is_negated(old_lit):
return 0
return 1
# here we have GF fair -> GF just
res = aiglib.get_ith_fairness(spec, 0).lit
if is_negated(old_lit):
res = negate(res)
return res
return old_lit + shift
def main(filename):
#: :type: aiglib.aiger
model = aiglib.aiger_init()
aiglib.aiger_open_and_read_from_file(model, filename)
if model.num_justice == 0:
_write_result(model)
return
assert model.num_justice == 1
assert model.justice.size == 1
next_lit = (model.maxvar + 1) * 2
# first, add all elements
aiglib.aiger_add_input(model, next_lit, 'SYNT_2_HWMCC_aux')
#: :type: aiglib.aiger_symbol
aux = aiglib.aiger_is_input(model, next_lit)
next_lit += 2
aiglib.aiger_add_and(model, next_lit, 1, 1)
#: :type: aiglib.aiger_and
and1 = aiglib.aiger_is_and(model, next_lit)
next_lit += 2
aiglib.aiger_add_and(model, next_lit, 1, 1)
#: :type: aiglib.aiger_and
and2 = aiglib.aiger_is_and(model, next_lit)
next_lit += 2
aiglib.aiger_add_and(model, next_lit, 1, 1)
#: :type: aiglib.aiger_and
and3 = aiglib.aiger_is_and(model, next_lit)
next_lit += 2
aiglib.aiger_add_and(model, next_lit, 1, 1)
#: :type: aiglib.aiger_and
and4 = aiglib.aiger_is_and(model, next_lit)
next_lit += 2
aiglib.aiger_add_latch(model, next_lit, 1, 'SYNT_2_HWMCC_L1')
#: :type: aiglib.aiger_and
L1 = aiglib.aiger_is_latch(model, next_lit)
next_lit += 2
aiglib.aiger_add_latch(model, next_lit, 1, 'SYNT_2_HWMCC_L2')
#: :type: aiglib.aiger_and
L2 = aiglib.aiger_is_latch(model, next_lit)
next_lit += 2
#: :type: aiglib.aiger_symbol
old_just_lit = aiglib.get_justice_lit(model, 0, 0)
# second, define all connections
and1.rhs0, and1.rhs1 = aux.lit + 1, L1.lit + 1
and2.rhs0, and2.rhs1 = L1.lit, old_just_lit
and3.rhs0, and3.rhs1 = and2.lhs + 1, L2.lit + 1
and4.rhs0, and4.rhs1 = L2.lit + 1, L1.lit
L1.next = and1.lhs + 1
L2.next = and3.lhs + 1
aiglib.set_justice_lit(model, 0, 0, and4.lhs)
#
_write_result(model)
def main(filename):
#: :type: aiglib.aiger
model = aiglib.aiger_init()
aiglib.aiger_open_and_read_from_file(model, filename)
if model.num_justice == 0:
_write_result(model)
return
assert model.num_justice == 1
assert model.justice.size == 1
next_lit = (model.maxvar + 1) * 2
# first, add all elements
aiglib.aiger_add_input(model, next_lit, 'SYNT_2_HWMCC_aux')
#: :type: aiglib.aiger_symbol
aux = aiglib.aiger_is_input(model, next_lit)
next_lit += 2
aiglib.aiger_add_and(model, next_lit, 1, 1)
#: :type: aiglib.aiger_and
and1 = aiglib.aiger_is_and(model, next_lit)
next_lit += 2
aiglib.aiger_add_and(model, next_lit, 1, 1)
#: :type: aiglib.aiger_and
and2 = aiglib.aiger_is_and(model, next_lit)
next_lit += 2
aiglib.aiger_add_and(model, next_lit, 1, 1)
#: :type: aiglib.aiger_and
and3 = aiglib.aiger_is_and(model, next_lit)
next_lit += 2
aiglib.aiger_add_and(model, next_lit, 1, 1)
#: :type: aiglib.aiger_and
and4 = aiglib.aiger_is_and(model, next_lit)
next_lit += 2
aiglib.aiger_add_latch(model, next_lit, 1, 'SYNT_2_HWMCC_L1')
#: :type: aiglib.aiger_and
L1 = aiglib.aiger_is_latch(model, next_lit)
next_lit += 2
aiglib.aiger_add_latch(model, next_lit, 1, 'SYNT_2_HWMCC_L2')
#: :type: aiglib.aiger_and
L2 = aiglib.aiger_is_latch(model, next_lit)
next_lit += 2
#: :type: aiglib.aiger_symbol
old_just_lit = aiglib.get_justice_lit(model, 0, 0)
# second, define all connections
and1.rhs0, and1.rhs1 = aux.lit + 1, L1.lit + 1
and2.rhs0, and2.rhs1 = L1.lit, old_just_lit
and3.rhs0, and3.rhs1 = and2.lhs + 1, L2.lit + 1
and4.rhs0, and4.rhs1 = L2.lit + 1, L1.lit
L1.next = and1.lhs + 1
L2.next = and3.lhs + 1
aiglib.set_justice_lit(model, 0, 0, and4.lhs)
#
_write_result(model)
