def test_find_two_small_file_duplicates(self):
response = dff('test/two_small_duplicates')
self.assertRegex(
response, 'bbb.txt\n is dupe of test.two_small_duplicates.aaa.txt')
self.assertRegex(
response, 'ccc.txt\n is dupe of test.two_small_duplicates.aaa.txt')
self.assertNotRegex(response, 'aaa.txt\n is dupe of')
def test_find_large_file_duplicate(self):
response = dff('test/one_large_duplicate')
self.assertRegex(
response,
'big bbb.txt\n is dupe of test.one_large_duplicate.big aaa.txt')
self.assertRegex(response, 'calculating full hash')
self.assertNotRegex(response, 'big aaa.txt\n is dupe')
def test_find_two_large_file_duplicates(self):
response = dff('test/two_large_duplicates')
self.assertRegex(
response,
'big bbb.txt\n is dupe of test.two_large_duplicates.big aaa.txt')
self.assertRegex(
response,
'big ccc.txt\n is dupe of test.two_large_duplicates.big aaa.txt')
self.assertNotRegex(response, 'big aaa.txt\n is dupe')
def bench(self):
q, d, clk, reset = [Signal(intbv(0)) for i in range(4)]
DFF_1 = dff(q, d, clk, reset)
CLK_1 = self.clkGen(clk)
ST_1 = self.stimulus(d, clk, reset)
CH_1 = self.check(q, clk, reset)
sim = Simulation(DFF_1, CLK_1, ST_1, CH_1)
return sim
def bench(self):
q, d, clk, reset = [Signal(intbv(0)) for i in range(4)]
DFF_1 = dff(q, d, clk, reset)
CLK_1 = self.clkGen(clk)
ST_1 = self.stimulus(d, clk, reset)
CH_1 = self.check(q, clk, reset)
sim = Simulation(DFF_1, CLK_1, ST_1, CH_1)
return sim
def dff_clkout(clkout, q, d, clk, reset):
DFF_1 = dff(q, d, clkout, reset)
@instance
def assign():
while 1:
yield clk
clkout.next = clk
return DFF_1, assign
def dff_clkout(clkout, q, d, clk, reset):
DFF_1 = dff(q, d, clkout, reset)
@instance
def assign():
while 1:
yield clk
clkout.next = clk
return DFF_1, assign
def test_delete_duplicates_trial(self):
response = dff('test/duplicate_across_folders', True)
self.assertRegex(
response,
'deleted ... test.duplicate_across_folders.sub1.dupe.txt')
self.assertRegex(
response,
'deleted ... test.duplicate_across_folders.sub1.supersub.also_dupe.txt'
)
self.assertRegex(
response,
'deleted ... test.duplicate_across_folders.sub2.dupe.txt')
def test_duplicate_across_folders(self):
response = dff('test/duplicate_across_folders')
self.assertRegex(
response,
'sub1.dupe.txt\n is dupe of test.duplicate_across_folders.master.txt'
)
self.assertRegex(
response,
'sub1.supersub.also_dupe.txt\n is dupe of test.duplicate_across_folders.master.txt'
)
self.assertRegex(
response,
'sub2.dupe.txt\n is dupe of test.duplicate_across_folders.master.txt'
)
def test_dff():
q, d, clk = [Signal(bool(0)) for i in range(3)]
dff_inst = dff(q, d, clk)
@always(delay(10))
def clkgen():
clk.next = not clk
@always(clk.negedge)
def stimulus():
d.next = randrange(2)
return dff_inst, clkgen, stimulus
def test_delete_file_with_longest_name(self):
shutil.rmtree("test/delete_filename_length", ignore_errors=True)
shutil.rmtree("test/delete_filename_length", ignore_errors=True)
shutil.rmtree("test/delete_filename_length", ignore_errors=True)
shutil.copytree("test/filename_length", "test/delete_filename_length")
set_delete_shorter(True)
set_trial_delete(False)
response = dff("test/delete_filename_length", True)
set_delete_shorter(False)
set_trial_delete(True)
self.assertRegex(response, "deleted ... test.delete_filename_length.bbbb.txt")
self.assertRegex(response, "deleted ... test.delete_filename_length.cc.txt")
self.assertRegex(response, "aaaaaa.txt ... deleted")
self.assertRegex(response, "deleted ... test.delete_filename_length.ee.txt")
self.assertRegex(response, "aaaaaa.txt ... already deleted")
self.assertRegex(response, "failed to delete 1 duplicates - rerun script")
def ReadWriteFlipFlop(t, dir, wr, rst):
""" A scalable Tri-State Buffer
I/O pins:
--------
t : tristated buffer the data comes in on and leaves out.
dir : input; signal driving direction of tristate buffer.
wr : input; signal indicating when to latch data.
rst : input; signal indicating clear of latch data.
"""
i = Signal(intbv(0)[len(t):])
q = Signal(intbv(0)[len(t):])
data = InOutBuffer(t, i, q, dir)
dff_inst = dff(q, i, wr, rst)
return data, dff_inst
def test_delete_read_only_file(self):
try:
os.chmod("test/delete_unit_test/bbb.txt", stat.S_IWRITE)
except FileNotFoundError:
pass
# Why is this so unreliable ???
shutil.rmtree("test/delete_unit_test", ignore_errors=True)
shutil.rmtree("test/delete_unit_test", ignore_errors=True)
shutil.rmtree("test/delete_unit_test", ignore_errors=True)
try:
shutil.copytree("test/one_small_duplicate", "test/delete_unit_test")
except PermissionError:
print("Got some really wierd permission error - try again")
shutil.copytree("test/one_small_duplicate", "test/delete_unit_test")
os.chmod("test/delete_unit_test/bbb.txt", S_IREAD | S_IRGRP | S_IROTH)
set_trial_delete(False)
response = dff("test/delete_unit_test", True)
set_trial_delete(True)
self.assertRegex(response, "deleted ... test.delete_unit_test.bbb.txt")
def test_find_two_small_file_duplicates(self):
response = dff("test/two_small_duplicates")
self.assertRegex(response, "bbb.txt\n is dupe of test.two_small_duplicates.aaa.txt")
self.assertRegex(response, "ccc.txt\n is dupe of test.two_small_duplicates.aaa.txt")
self.assertNotRegex(response, "aaa.txt\n is dupe of")
def test_do_not_find_many_large_files_almost_duplicate(self):
response = dff("test/many_large_almost_duplicate")
self.assertNotRegex(response, "is dupe of")
self.assertRegex(response, "but files are different")
def test_find_large_file_duplicate(self):
response = dff("test/one_large_duplicate")
self.assertRegex(response, "big bbb.txt\n is dupe of test.one_large_duplicate.big aaa.txt")
self.assertRegex(response, "calculating full hash")
self.assertNotRegex(response, "big aaa.txt\n is dupe")
#!/usr/bin/env python import sys import dff import numpy def computeStrainRate(dffs): time = [] relstrain = [] for dff in dffs: relstrain.append(dff.get_averagestrain()) time.append(dff.get_time()) f = numpy.polyfit(time, relstrain,1) return f[0] sys.argv.pop(0) deformations = [] for i in range(0, len(sys.argv)): deformations.append(dff.dff(sys.argv[i])) running = [] running.append(deformations.pop(0)) running.append(deformations.pop(0)) running.append(deformations.pop(0)) running.append(deformations.pop(0)) running.append(deformations.pop(0)) while deformations: print running[2].get_time(), computeStrainRate(running), running[2].get_averagestrain() running.append(deformations.pop(0)) running.pop(0)
def test_find_small_file_duplicate(self):
response = dff('test/one_small_duplicate')
self.assertRegex(response, 'calculating hash snippet')
self.assertRegex(
response, 'bbb.txt\n is dupe of test.one_small_duplicate.aaa.txt')
def test_ignore_zero_byte_files(self):
response = dff("test/two_zero_byte_files")
self.assertNotRegex(response, "Processing file")
self.assertNotRegex(response, "is dupe of")
#!/usr/bin/env python
import sys
import dff
def correlation(Zh, l):
count = 0.0
sum = 0.0
for i in range(0, Zh.shape[1]-l-1):
for j in range(0, Zh.shape[0]-1):
sum = sum + (Zh[j,i]-Zh[j,i+l])**2
count = count + 1
# print sum, count
sum = sum / count
return sum
sys.argv.pop(0)
name = sys.argv.pop(0)
for l in range(1, 5,1):
fd = open(name + "." + str(l) + ".dat", 'w')
for i in range(0, len(sys.argv)):
deformation = dff.dff(sys.argv[i])
relativestrains = deformation.get_relativestrain()
fd.write("%lf %e\n" % (deformation.get_time(), correlation(relativestrains, l)));
fd.close()
def test_do_not_process_file_of_unique_byte_size(self):
response = dff('test/different_file_sizes')
self.assertNotRegex(response, 'Processing file')
def test_files_with_non_unique_file_size_added_to_process_list(self):
response = dff('test/one_large_almost_duplicate')
self.assertRegex(response, 'big bbb.txt added to process list')
self.assertRegex(response, 'big aaa.txt added to process list')
self.assertRegex(response, 'has non unique')
def test_show_start_and_end_times(self):
response = dff('test/duplicate_across_folders')
self.assertRegex(response, '\d{2}:\d{2}:\d{2}')
def test_show_run_time_in_seconds(self):
response = dff('test/duplicate_across_folders')
self.assertRegex(response, 'in \d+\.\d+ seconds')
def test_search_sub_folders(self):
response = dff("test")
self.assertRegex(response, "is dupe of")
self.assertRegex(response, "but files are different")
def main(argv):
inputfile = ''
outputfile = ''
verbose = False
try:
opts, args = getopt.getopt(argv,"hvi:o:f:",["ifile=","ofile="])
except getopt.GetoptError:
print 'usage: bench2vhdl.py -i <inputfile> -o <outputfile>'
sys.exit(2)
for opt, arg in opts:
if opt == '-h':
print 'usage: bench2vhdl.py -i <inputfile> -o <outputfile>'
sys.exit()
elif opt in ("-v", "--verbose"):
verbose = True
elif opt in ("-i", "--ifile"):
inputfile = arg
elif opt in ("-o", "--ofile"):
outputfile = arg
# Initialize lists for inputs, outputs, FFs and gates
l_statistics = []
l_inputs = []
l_outputs = []
l_dffs = []
l_inverters = []
l_and_gates = []
l_nand_gates = []
l_or_gates = []
l_nor_gates = []
l_connections = []
verbosity_level = '1'
# Print some information for the user if verbose made has been activated
if verbose == True:
print 'This is bench2vhdl; verbose mode activated'
print 'Input file is:', inputfile
print 'Output file is:', outputfile
###############################################################
# PROCESS .BENCH INPUT FILE #
###############################################################
entityname = os.path.basename(inputfile)
entityname = entityname[0:entityname.find('.')]
if verbose == True:
print 'Parsing input file for entity %s .....' % entityname
with open(inputfile) as f:
for line in f:
# Skip comment lines
if line.startswith('#') == True:
l_statistics.append('--% s' % line)
#print 'comment detected: %s' % line
# Detect inputs
if line.startswith('INPUT') == True:
open_bracket = line.find('(')+1
close_bracket = line.find(')')
l_inputs.append(line[open_bracket:close_bracket])
# Detect outputs
elif line.startswith('OUTPUT') == True:
open_bracket = line.find('(')+1
close_bracket = line.find(')')
l_outputs.append(line[open_bracket:close_bracket])
#Processing of D flip-flops
elif 'DFF' in line:
open_bracket = line.find('(')+1
close_bracket = line.find(')')
D_in = line[open_bracket:close_bracket]
if not(D_in.strip() in l_connections):
l_connections.append(D_in.strip())
Q_out = line[0:line.find('=')-1]
if not(Q_out.strip() in l_connections):
l_connections.append(Q_out.strip())
new_dff = dff(D_in, Q_out, 'clk', 'reset')
l_dffs.append(new_dff)
elif 'NOT' in line:
open_bracket = line.find('(')+1
close_bracket = line.find(')')
A = line[open_bracket:close_bracket]
if not (A.strip() in l_connections):
l_connections.append(A.strip())
Z = line[0:line.find('=')-1]
if not (Z.strip() in l_connections):
l_connections.append(Z.strip())
new_inverter = lis_not(A,Z)
l_inverters.append(new_inverter)
elif 'AND' in line and not 'NAND' in line and not '#' in line:
open_bracket = line.find('(')+1
close_bracket = line.find(')')
gate_size = line.count(',', open_bracket, close_bracket) + 1
Z = line[0:line.find('=')-1]
if not(Z.strip() in l_connections):
l_connections.append(Z.strip())
if gate_size == 2:
l_input_ports = line[open_bracket:close_bracket].split(',')
new_and2 = and2(l_input_ports[0].strip(), l_input_ports[1].strip(), Z)
l_and_gates.append(new_and2)
elif gate_size == 3:
l_input_ports = line[open_bracket:close_bracket].split(',')
new_and3 = lis_and3(l_input_ports[0].strip(), l_input_ports[1].strip(), l_input_ports[2].strip(), Z)
l_and_gates.append(new_and3)
elif gate_size == 4:
l_input_ports = line[open_bracket:close_bracket].split(',')
new_and4 = lis_and4(l_input_ports[0].strip(), l_input_ports[1].strip(), l_input_ports[2].strip(), l_input_ports[3].strip(), Z)
l_and_gates.append(new_and4)
for signal in l_input_ports:
if not(signal.strip() in l_connections):
l_connections.append(signal.strip())
elif 'OR' in line and not 'NOR' in line and not '#' in line:
open_bracket = line.find('(')+1
close_bracket = line.find(')')
gate_size = line.count(',', open_bracket, close_bracket) + 1
Z = line[0:line.find('=')-1]
if not(Z.strip() in l_connections):
l_connections.append(Z.strip())
if gate_size == 2:
l_input_ports = line[open_bracket:close_bracket].split(',')
new_or2 = lis_or2(l_input_ports[0].strip(), l_input_ports[1].strip(), Z)
l_or_gates.append(new_or2)
elif gate_size == 3:
l_input_ports = line[open_bracket:close_bracket].split(',')
new_or3 = lis_or3(l_input_ports[0].strip(), l_input_ports[1].strip(), l_input_ports[2].strip(), Z)
l_or_gates.append(new_or3)
elif gate_size == 4:
l_input_ports = line[open_bracket:close_bracket].split(',')
new_or4 = lis_or4(l_input_ports[0].strip(), l_input_ports[1].strip(), l_input_ports[2].strip(), l_input_ports[3].strip(), Z)
l_or_gates.append(new_or4)
for signal in l_input_ports:
if not(signal.strip() in l_connections):
l_connections.append(signal.strip())
elif 'NAND' in line and not '#' in line:
open_bracket = line.find('(')+1
close_bracket = line.find(')')
gate_size = line.count(',', open_bracket, close_bracket) + 1
Z = line[0:line.find('=')-1]
if not(Z.strip() in l_connections):
l_connections.append(Z.strip())
if gate_size == 2:
l_input_ports = line[open_bracket:close_bracket].split(',')
new_nand2 = lis_nand2(l_input_ports[0].strip(), l_input_ports[1].strip(), Z)
l_nand_gates.append(new_nand2)
elif gate_size == 3:
l_input_ports = line[open_bracket:close_bracket].split(',')
new_nand3 = lis_nand3(l_input_ports[0].strip(), l_input_ports[1].strip(), l_input_ports[2].strip(), Z)
l_nand_gates.append(new_nand3)
elif gate_size == 4:
l_input_ports = line[open_bracket:close_bracket].split(',')
new_nand4 = lis_nand4(l_input_ports[0].strip(), l_input_ports[1].strip(), l_input_ports[2].strip(), l_input_ports[3].strip(), Z)
l_nand_gates.append(new_nand4)
for signal in l_input_ports:
if not(signal.strip() in l_connections):
l_connections.append(signal.strip())
elif 'NOR' in line and not '#' in line:
open_bracket = line.find('(')+1
close_bracket = line.find(')')
gate_size = line.count(',', open_bracket, close_bracket) + 1
Z = line[0:line.find('=')-1]
if not(Z.strip() in l_connections):
l_connections.append(Z.strip())
if gate_size == 2:
l_input_ports = line[open_bracket:close_bracket].split(',')
new_nor2 = lis_nor2(l_input_ports[0].strip(), l_input_ports[1].strip(), Z)
l_nor_gates.append(new_nor2)
elif gate_size == 3:
l_input_ports = line[open_bracket:close_bracket].split(',')
new_nor3 = lis_nor3(l_input_ports[0].strip(), l_input_ports[1].strip(), l_input_ports[2].strip(), Z)
l_nor_gates.append(new_nor3)
elif gate_size == 4:
l_input_ports = line[open_bracket:close_bracket].split(',')
new_nor4 = lis_nor4(l_input_ports[0].strip(), l_input_ports[1].strip(), l_input_ports[2].strip(), l_input_ports[3].strip(), Z)
l_nor_gates.append(new_nor4)
for signal in l_input_ports:
if not(signal.strip() in l_connections):
l_connections.append(signal.strip())
if verbose == True:
print 'Done\n\nThe following elements have been found in the design:'
print '%d inputs: %s' % ( len(l_inputs), l_inputs)
print '%d outputs: %s' % ( len(l_outputs), l_outputs)
print '%d D flip-flops' % len(l_dffs)
print '%d inverters' % len(l_inverters)
print '%d logic gates: %d ANDs, %d NANDs, %d ORs, %d NORs\n' % ( len(l_and_gates) + len(l_nand_gates) + len(l_or_gates) + len(l_nor_gates), len(l_and_gates), len(l_nand_gates), len(l_or_gates), len(l_nor_gates) )
# Post processing of l_connections
for signal in l_connections:
if signal in l_inputs or signal in l_outputs:
l_connections.remove(signal)
f.close
###############################################################
# CREATE VHDL DESCRIPTION OF THE CIRCUIT #
###############################################################
# Open outputfile in write mode
target = open(outputfile, 'w')
# Write header with author information and statistics
#entityname = inputfile[0:inputfile.find('.')]
now = datetime.datetime.now()
target.write('------------------------------------------------------------------------\n')
target.write('--#LIS#\n')
target.write('--Author: Sebastian Kroesche\n')
target.write('--Date: %02d.%02d.%d \n' % (now.day, now.month, now.year) )
target.write('--Description: Implementation of ISCAS89 %s circuit with\n' % entityname)
target.write('-- D-type flip-flops\n')
target.write('-- generated with bench2vhdl\n')
target.write('--Circuit statistics\n')
for statline in l_statistics:
target.write(statline)
target.write('------------------------------------------------------------------------\n')
# Write library imports to outputfile
target.write('library IEEE;\nuse IEEE.std_logic_1164.all; \n \n')
target.write('library lis_lib;\nuse lis_lib.ser_bist.all; \n \n')
#Write entity declaration to outputfile
target.write('entity %s is\n' % entityname)
target.write('\tport (\n')
target.write('\t\tclk : in std_logic; \n')
target.write('\t\treset : in std_logic; \n')
for input_port in l_inputs:
#target.write(input_port)
target.write('\t\t%s: in std_logic; \n' % input_port)
for i in range(0, len(l_outputs)-1):
target.write('\t\t%s: out std_logic; \n' % l_outputs[i])
target.write('\t\t%s: out std_logic \n' % l_outputs[len(l_outputs)-1])
target.write('\t);\n')
target.write('end entity; \n\n')
#Write opening line of architecture
target.write('architecture rtl of %s is\n\n' % entityname)
#Write interconnecting signals
for signal in l_connections:
target.write('\tsignal %s : std_logic;\n' % signal)
#Write begin of architecture
target.write('\nbegin\n')
#Write flip-flops
target.write('\n--Flip-flops (total number: %d)\n' % len(l_dffs))
for i in range(0, len(l_dffs)):
target.write('DFF_%d:\t lis_dff port map( clk => clk, Q_out => %s, D_in => % s, reset => reset );\n' % (i, l_dffs[i].Q_out, l_dffs[i].D_in) )
target.write('\n--Inverters (total number: %d)\n'% len(l_inverters))
#Write inverters
for i in range(0, len(l_inverters)):
target.write('INV_%d:\t lis_not port map( A => %s, Z => %s );\n' % (i, l_inverters[i].A, l_inverters[i].Z) )
#Write AND-gates
target.write('\n--AND-gates (total number: %d)\n' % len(l_and_gates))
for i in range(0, len(l_and_gates)):
if isinstance(l_and_gates[i], and2):
target.write(and2.writePortMap(l_and_gates[i]))
elif isinstance(l_and_gates[i], lis_and3):
target.write(lis_and3.writePortMap(l_and_gates[i]))
elif isinstance(l_and_gates[i], lis_and4):
target.write(lis_and4.writePortMap(l_and_gates[i]))
#Write OR-gates
target.write('\n--OR-gates (total number: %d)\n' % len(l_or_gates))
for i in range(0, len(l_or_gates)):
if isinstance(l_or_gates[i], lis_or2):
target.write(lis_or2.writePortMap(l_or_gates[i]))
elif isinstance(l_or_gates[i], lis_or3):
target.write(lis_or3.writePortMap(l_or_gates[i]))
elif isinstance(l_or_gates[i], lis_or4):
target.write(lis_or4.writePortMap(l_or_gates[i]))
#Write NAND-gates
target.write('\n--NAND-gates (total number: %d)\n' % len(l_nand_gates))#
for i in range(0, len(l_nand_gates)):
if isinstance(l_nand_gates[i], lis_nand2):
target.write(lis_nand2.writePortMap(l_nand_gates[i]))
elif isinstance(l_nand_gates[i], lis_nand3):
target.write(lis_nand3.writePortMap(l_nand_gates[i]))
elif isinstance(l_nand_gates[i], lis_nand4):
target.write(lis_nand4.writePortMap(l_nand_gates[i]))
#Write NOR-gates
target.write('\n--NOR-gates (total number: %d)\n' % len(l_nor_gates))
for i in range(0, len(l_nor_gates)):
if isinstance(l_nor_gates[i], lis_nor2):
target.write(lis_nor2.writePnortMap(l_nor_gates[i]))
elif isinstance(l_nor_gates[i], lis_nor3):
target.write(lis_nor3.writePnortMap(l_nor_gates[i]))
elif isinstance(l_nor_gates[i], lis_nor4):
target.write(lis_nor4.writePnortMap(l_nor_gates[i]))
target.write('\nend architecture;\n')
target.close
if verbose == True and verbosity_level == '2':
print '\nThe following VHDL design has been created from the inputfile:\n'
target = open(outputfile, 'r')
for line in target:
print line[0:len(line)-1]
###############################################################
# CREATE STUCK-AT-FAULT DESCRIPTION FILE #
###############################################################
# Open outputfile in write mode
faultfile = '%s.fdf' % entityname
target = open(faultfile, 'w')
# Write header with author information and statistics
target.write('# Stuck-at-fault description file for circuit %s\n' % entityname)
target.write('# Created by bench2vhdl on %d-%02d-%02d\n' % (now.year, now.month, now.day) )
# target.write('signal_name;s-a-1 det;s-a-0 det\n')
for signal in l_inputs:
target.write('%s\n' % signal)
for signal in l_outputs:
target.write('%s\n' % signal)
# target.write('#;#;#\n')
for signal in l_connections:
target.write('%s\n' % signal)
target.close
if verbose == True:
print 'stuck-at-fault description file written to %s' % faultfile
def test_show_megabytes_scanned(self):
response = dff('test/duplicate_across_folders')
self.assertRegex(response, '0.046875 megabytes scanned')
def test_do_not_find_many_large_files_almost_duplicate(self):
response = dff('test/many_large_almost_duplicate')
self.assertNotRegex(response, 'is dupe of')
self.assertRegex(response, 'but files are different')
def test_known_duplicates_not_added_to_list_multiple_times(self):
response = dff('test/two_small_duplicates')
self.assertRegex(response, 'aaa.txt is a known size duplicate')
self.assertRegex(response, 'aaa.txt added to process list')
self.assertRegex(response, 'bbb.txt added to process list')
self.assertRegex(response, 'ccc.txt added to process list')
def test_search_sub_folders(self):
response = dff('test')
self.assertRegex(response, 'is dupe of')
self.assertRegex(response, 'but files are different')
def test_ignore_zero_byte_files(self):
response = dff('test/two_zero_byte_files')
self.assertNotRegex(response, 'Processing file')
self.assertNotRegex(response, 'is dupe of')
def test_show_count_of_duplicates(self):
response = dff('test/duplicate_across_folders')
self.assertRegex(response, '3 duplicate files found')
def test_verbose_output_enabled(self):
response = dff('test/one_file')
self.assertRegex(response, 'Checking size of file')
def test_count_of_examined_files(self):
response = dff('test/duplicate_across_folders')
self.assertRegex(response, '4 files and')
def convert(hdl):
q, d, clk = [Signal(bool(0)) for i in range(3)]
inst = dff(q, d, clk)
inst.convert(hdl=hdl)
