示例#1
0
文件: ddc.py 项目: n8ohu/whitebox
def cic_decim(clearn, clock,
        in_sign,
        out_sign,
        decim,
        #shift,
        cic_order=4, cic_delay=2, **kwargs):
    """A cic decimating filter with given order and delay.

    :param clearn: Reset the filter.
    :param clock: The clock.
    :param in_sign: The input signature.
    :param out_sign: The output signature.
    :param decim: The decimation of the cic filter.
    :param shift: How much to shift the result.
    :param cic_order: The order of the CIC filter.
    :param cic_delay: The delay of the CIC comb elements.
    :returns: A synthesizable MyHDL instance.
    """
    in_valid = in_sign.valid
    in_i = in_sign.i
    in_q = in_sign.q
    in_last = in_sign.last
    out_last = out_sign.last
    out_valid = out_sign.valid
    out_i = out_sign.i
    out_q = out_sign.q
    rates = kwargs.get('rates', [decim])
    max_rate = max(rates)

    accumed = [Signature('accumed_%d' % i, True, bits=cic_decim_register_width(
            len(in_i), len(out_i), max_rate, cic_order, cic_delay,
            i)) for i in range(1, cic_order + 1)]
    print 'accumed', accumed
    combed = [Signature('combed_%d' % i, True, bits=cic_decim_register_width(
            len(in_i), len(out_i), max_rate, cic_order, cic_delay,
            cic_order + i)) for i in range(1, cic_order + 1)]
    print 'combed', combed

    accums = []
    for n in range(cic_order):
        if n == 0:
            i = in_sign
        else:
            i = accumed[n - 1]

        o = accumed[n]

        print 'accum in=%d, out=%d' % (len(i.q), len(o.q))
        accums.append(accumulator(clearn, clock, i, o, n))  # TODO truncate

    decimated = accumed[cic_order - 1].copy('decimated')
    decimator_0 = downsampler(clearn, clock,
        accumed[cic_order - 1], decimated,
        decim)

    combs = []
    for n in range(cic_order):
        if n == 0:
            i = decimated
        else:
            i = combed[n - 1]

        o = combed[n]

        print 'comb in=%d, out=%d' % (len(i.q), len(o.q))
        combs.append(comb(clearn, clock, cic_delay, i, o))  # TODO truncate
    
    # TODO: does this need a shifter?  yeah.
    truncator_0 = truncator(clearn, clock,
        combed[cic_order - 1], out_sign)

    instances = accums, decimator_0, combs, truncator_0

    if kwargs.get('sim', None):
        sim = kwargs['sim']
        sim.record(in_sign)
        [sim.record(a) for a in accumed]
        sim.record(decimated)
        [sim.record(c) for c in combed]
        sim.record(out_sign)

    return instances
示例#2
0
文件: duc.py 项目: n8ohu/whitebox
def cic(clearn, clock,
        in_sign,
        out_sign,
        interp,
        shift,
        cic_order=4, cic_delay=2, **kwargs):
    """A cic filter with given order, delay, and interpolation.

    :param clearn: The reset the accumulator.
    :param clock: The clock.
    :param in_sign: The input signature.
    :param out_sign: The output signature.
    :param interp: The interpolation of the cic filter.
    :param cic_order: The order of the CIC filter.
    :param cic_delay: The delay of the CIC comb elements.
    :returns: A synthesizable MyHDL instance.
    """
    in_valid = in_sign.valid
    in_i = in_sign.i
    in_q = in_sign.q
    in_last = in_sign.last
    out_last = out_sign.last
    out_valid = out_sign.valid
    out_i = out_sign.i
    out_q = out_sign.q
    rates = kwargs.get('rates', [interp])
    max_rate = max(rates)

    #print 'CIC order=%d delay=%d interp=%d' % (cic_order, cic_delay, interp)

    combed = [Signature('combed_%d' % i, True, bits=cic_bit_width(
            len(in_i), max_rate, cic_order, cic_delay,
            i)) for i in range(1, cic_order + 1)]
    accumed = [Signature('accumed_%d' % i, True, bits=cic_bit_width(
            len(in_i), max_rate, cic_order, cic_delay,
            cic_order + i)) for i in range(1, cic_order + 1)]

    combs = []
    for n in range(cic_order):
        if n == 0:
            i = in_sign # interpolated
        else:
            i = combed[n - 1]

        o = combed[n]

        #print 'comb stage', n, i, '->', o

        combs.append(comb(clearn, clock, cic_delay, i, o))

    interpolated = combed[cic_order - 1].copy('interpolated')
    interpolator_0 = interpolator(clearn, clock,
        combed[cic_order - 1], interpolated,
        interp)

    #print 'interpolator', combed[cic_order - 1], '->', interpolated

    accums = []
    for n in range(cic_order):
        if n == 0:
            i = interpolated #combed[cic_order - 1]
        else:
            i = accumed[n - 1]

        o = accumed[n]

        #print 'accum stage', n, i, '->', o

        accums.append(accumulator(clearn, clock, i, o))

    #print 'decimated', accumed[cic_order - 1], '->', out_sign

    #truncator_2 = truncator(clearn, clock,
    #    accumed[cic_order - 1], out_sign, debug=True)
    shifter_0 = shifting_truncator(clearn, clock,
          accumed[cic_order - 1], out_sign,
          shift)
    
    instances = combs, interpolator_0, accums, shifter_0 #truncator_2

    # NOTE: This only works when used with MyHDL's Simulation
    # feature, not Cosimulation with an external Verilog tool.
    # So, for the Whitebox codebase, this means DSP tests can use
    # it but not Cosimulations of the Whitebox toplevel HDL.
    if kwargs.get('sim', None):
        sim = kwargs['sim']
        sim.record(in_sign)
        [sim.record(c) for c in combed]
        sim.record(interpolated)
        [sim.record(a) for a in accumed]
        sim.record(out_sign)

    return instances