def test_files(tool):
prj = Project(tool)
prj.add_files(get_path('../hdl/*.vhdl'))
prj.add_files(get_path('../hdl/*.v'))
assert len(prj.get_files()['verilog']) == 3
assert len(prj.get_files()['vhdl']) == 4
assert len(prj.get_files()['constraint']) == 0
parser.add_argument(
'--action', choices=['generate', 'transfer', 'all'], default='generate',
)
parser.add_argument(
'--lang', choices=['verilog', 'vhdl'], default='verilog',
)
args = parser.parse_args()
prj = Project('openflow')
prj.set_outdir('../../build/icestorm-{}'.format(args.lang))
prj.set_part('hx4k-tq144')
if args.lang == 'verilog':
prj.add_path('../../hdl/headers1')
prj.add_path('../../hdl/headers2')
prj.add_files('../../hdl/blinking.v')
prj.add_files('../../hdl/top.v')
else: # args.lang == 'vhdl'
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.add_files('*.pcf')
prj.set_top('Top')
if args.action in ['generate', 'all']:
try:
prj.generate()
except RuntimeError:
print('ERROR:generate:Docker not found')
"""PyFPGA example about Memory Content Files inclusion.
This example is mainly used as a test of this feature through the different
tools.
"""
import logging
from fpga.project import Project, TOOLS
logging.basicConfig()
for hdl in ['vhdl', 'verilog']:
for tool in TOOLS:
if tool == 'ghdl' and hdl == 'verilog':
continue
PRJ = Project(tool)
PRJ.set_outdir('../../build/multi/memory/%s/%s' % (tool, hdl))
if hdl == 'vhdl':
PRJ.add_files('../../hdl/ram.vhdl')
else:
PRJ.add_files('../../hdl/ram.v')
PRJ.set_top('ram')
try:
PRJ.generate(to_task='syn')
except RuntimeError:
print('ERROR:generate:{} not found'.format(tool))
)
parser.add_argument(
'--lang',
choices=['verilog', 'vhdl'],
default='verilog',
)
args = parser.parse_args()
prj = Project('yosys-vivado')
prj.set_outdir('../../build/yosys-vivado-{}'.format(args.lang))
prj.set_part('xc7z010-1-clg400')
if args.lang == 'verilog':
prj.add_path('../../hdl/headers1')
prj.add_path('../../hdl/headers2')
prj.add_files('../../hdl/blinking.v')
prj.add_files('../../hdl/top.v')
else: # args.lang == 'vhdl'
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.add_files('../vivado/zybo.xdc')
prj.set_top('Top')
if args.action in ['generate', 'all']:
try:
prj.generate()
except RuntimeError:
print('ERROR:generate:Docker or Vivado not found')
"""Zybo block design example project."""
import logging
from fpga.project import Project
logging.basicConfig()
prj = Project('vivado', 'zybo-design')
prj.set_part('xc7z010-1-clg400')
prj.set_outdir('../../build/zybo-design')
prj.add_files('../../hdl/blinking.vhdl')
prj.add_files('zybo.xdc')
prj.add_files('design.tcl', filetype='design')
export = """
set PROJECT %s
if { [ catch {
# Vitis
write_hw_platform -fixed -force -include_bit -file ${PROJECT}.xsa
} ] } {
# SDK
write_hwdef -force -file ${PROJECT}.hwdef
write_sysdef -force -hwdef [glob -nocomplain *.hwdef] \\
-bitfile [glob -nocomplain *.bit] -file ${PROJECT}.hdf
}
""" % ('zybo-design')
prj.add_hook(export, 'postbit')
default='orangecrab')
args = parser.parse_args()
BOARDS = {
'orangecrab': ['25k-CSFBGA285', 'orangecrab_r0.2.lpf'],
'ecp5evn': ['um5g-85k-CABGA381', 'ecp5evn.lpf']
}
prj = Project('openflow')
prj.set_outdir('../../build/prjtrellis-{}-{}'.format(args.board, args.lang))
prj.set_part(BOARDS[args.board][0])
if args.lang == 'verilog':
prj.add_path('../../hdl/headers1')
prj.add_path('../../hdl/headers2')
prj.add_files('../../hdl/blinking.v')
prj.add_files('../../hdl/top.v')
else: # args.lang == 'vhdl'
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.add_files(BOARDS[args.board][1])
prj.set_top('Top')
if args.action in ['generate', 'all']:
try:
prj.generate()
except RuntimeError:
print('ERROR:generate:Docker not found')
parser.add_argument(
'--action', choices=['generate', 'transfer', 'all'], default='generate',
)
parser.add_argument(
'--lang', choices=['verilog', 'vhdl'], default='verilog',
)
args = parser.parse_args()
prj = Project('yosys-ise')
prj.set_outdir('../../build/yosys-ise-{}'.format(args.lang))
prj.set_part('XC6SLX9-2-CSG324')
if args.lang == 'verilog':
prj.add_path('../../hdl/headers1')
prj.add_path('../../hdl/headers2')
prj.add_files('../../hdl/blinking.v')
prj.add_files('../../hdl/top.v')
else: # args.lang == 'vhdl'
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.add_files('../ise/s6micro.ucf')
prj.set_top('Top')
if args.action in ['generate', 'all']:
try:
prj.generate()
except RuntimeError:
print('ERROR:generate:Docker or ISE not found')
"""PyFPGA Multi Vendor VHDL example.
The main idea of a multi-vendor project is to implements the same HDL code
with different tools, to make comparisons. The project name is not important
and the default devices are used.
"""
import logging
from fpga.project import Project, TOOLS
logging.basicConfig()
for tool in TOOLS:
PRJ = Project(tool)
PRJ.set_outdir('../../build/multi/vhdl/%s' % tool)
PRJ.add_files('../../hdl/blinking.vhdl', library='examples')
PRJ.add_files('../../hdl/examples_pkg.vhdl', library='examples')
PRJ.add_files('../../hdl/top.vhdl')
PRJ.set_top('Top')
try:
PRJ.generate(to_task='syn')
except RuntimeError:
print('ERROR:generate:{} not found'.format(tool))
logging.basicConfig()
parser = argparse.ArgumentParser()
parser.add_argument(
'--action',
choices=['generate', 'transfer', 'all'],
default='generate',
)
args = parser.parse_args()
prj = Project('quartus')
prj.set_part('5CSEBA6U23I7')
prj.set_outdir('../../build/quartus')
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.set_top('Top')
prj.add_files('de10nano.sdc')
prj.add_files('de10nano.tcl')
if args.action in ['generate', 'all']:
try:
prj.generate()
except RuntimeError:
print('ERROR:generate:Quartus not found')
if args.action in ['transfer', 'all']:
try:
prj.transfer('fpga', 2)
"""PyFPGA Multi Vendor Verilog example.
The main idea of a multi-vendor project is to implements the same HDL code
with different tools, to make comparisons. The project name is not important
and the default devices could be used.
"""
import logging
from fpga.project import Project, TOOLS
logging.basicConfig()
for tool in TOOLS:
if tool == 'ghdl':
continue
PRJ = Project(tool)
PRJ.set_outdir('../../build/multi/verilog/%s' % tool)
PRJ.add_path('../../hdl/headers1')
PRJ.add_path('../../hdl/headers2')
PRJ.add_files('../../hdl/blinking.v')
PRJ.add_files('../../hdl/top.v')
PRJ.set_top('Top')
try:
PRJ.generate(to_task='syn')
except RuntimeError:
print('ERROR:generate:{} not found'.format(tool))
set_property strategy "Flow_PerfOptimized_high" $obj
set_property "steps.synth_design.args.fanout_limit" "400" $obj
set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj
set_property "steps.synth_design.args.resource_sharing" "off" $obj
set_property "steps.synth_design.args.no_lc" "1" $obj
set_property "steps.synth_design.args.shreg_min_size" "5" $obj
set obj [get_runs impl_1]
set_property strategy "Performance_Explore" $obj
set_property "steps.opt_design.args.directive" "Explore" $obj
set_property "steps.place_design.args.directive" "Explore" $obj
set_property "steps.phys_opt_design.is_enabled" "1" $obj
set_property "steps.phys_opt_design.args.directive" "Explore" $obj
set_property "steps.route_design.args.directive" "Explore" $obj
"""
}
}
for tool in commands:
for strategy in commands[tool]:
PRJ = Project(tool)
PRJ.set_outdir('../../build/hooks/%s-%s' % (tool, strategy))
PRJ.add_files('../../hdl/blinking.vhdl')
PRJ.set_top('Blinking')
PRJ.add_hook('puts "Appling {} optimizations"'.format(strategy),
'project')
PRJ.add_hook(commands[tool][strategy], 'project')
try:
PRJ.generate(to_task='syn')
except RuntimeError:
print('ERROR:generate:{} not found'.format(tool))
logging.basicConfig()
parser = argparse.ArgumentParser()
parser.add_argument(
'--action',
choices=['generate', 'transfer', 'all'],
default='generate',
)
args = parser.parse_args()
prj = Project('libero')
prj.set_part('m2s010-1-tq144')
prj.set_outdir('../../build/libero')
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.set_top('Top')
prj.add_files('mkr.pdc')
prj.add_files('mkr.sdc')
if args.action in ['generate', 'all']:
try:
prj.generate()
except RuntimeError:
print('ERROR:generate:Libero not found')
if args.action in ['transfer', 'all']:
print('ERROR:transfer:Not yet implemented')
parser = argparse.ArgumentParser()
parser.add_argument(
'--action',
choices=['generate', 'transfer', 'all'],
default='generate',
)
args = parser.parse_args()
prj = Project('vivado')
prj.set_part('xc7z010-1-clg400')
prj.set_outdir('../../build/vivado')
prj.set_param('FREQ', '125000000')
prj.add_files('../../hdl/blinking.vhdl')
prj.add_files('zybo.xdc')
prj.set_top('Blinking')
if args.action in ['generate', 'all']:
try:
prj.generate()
except RuntimeError:
print('ERROR:generate:Vivado not found')
if args.action in ['transfer', 'all']:
try:
prj.transfer('fpga')
except RuntimeError:
print('ERROR:transfer:Vivado not found')
