parser = argparse.ArgumentParser() parser.add_argument( '--action', choices=['generate', 'transfer', 'all'], default='generate', ) parser.add_argument( '--lang', choices=['verilog', 'vhdl'], default='verilog', ) args = parser.parse_args() prj = Project('openflow') prj.set_outdir('../../build/icestorm-{}'.format(args.lang)) prj.set_part('hx4k-tq144') if args.lang == 'verilog': prj.add_path('../../hdl/headers1') prj.add_path('../../hdl/headers2') prj.add_files('../../hdl/blinking.v') prj.add_files('../../hdl/top.v') else: # args.lang == 'vhdl' prj.add_files('../../hdl/blinking.vhdl', library='examples') prj.add_files('../../hdl/examples_pkg.vhdl', library='examples') prj.add_files('../../hdl/top.vhdl') prj.add_files('*.pcf') prj.set_top('Top') if args.action in ['generate', 'all']: try: prj.generate() except RuntimeError:
"""PyFPGA Multi Vendor Verilog example. The main idea of a multi-vendor project is to implements the same HDL code with different tools, to make comparisons. The project name is not important and the default devices could be used. """ import logging from fpga.project import Project, TOOLS logging.basicConfig() for tool in TOOLS: if tool == 'ghdl': continue PRJ = Project(tool) PRJ.set_outdir('../../build/multi/verilog/%s' % tool) PRJ.add_path('../../hdl/headers1') PRJ.add_path('../../hdl/headers2') PRJ.add_files('../../hdl/blinking.v') PRJ.add_files('../../hdl/top.v') PRJ.set_top('Top') try: PRJ.generate(to_task='syn') except RuntimeError: print('ERROR:generate:{} not found'.format(tool))