def test_one(self):
"""
Tests passing debug messages back.
"""
width = 32
sendnth = 2
max_val = pow(2, width-2)-1
n_data = 10
in_data = [random.randint(1, max_val) for i in range(n_data)]
defines = config.updated_defines({})
executable = buildutils.generate_icarus_executable(
'message', 'debug', '-test', defines=defines)
fpgaimage = buildutils.generate_B100_image(
'message', 'debug', '-test', defines=defines)
tb_icarus = TestBenchIcarusOuter(executable, in_raw=in_data,
sendnth=sendnth)
tb_b100 = TestBenchB100(fpgaimage, in_raw=in_data)
for tb, steps in (
#(tb_icarus, len(in_data)*sendnth*2+1000),
(tb_b100, 100000),
):
tb.run(steps)
r_samples, r_packets = msg_utils.stream_to_samples_and_packets(
tb.out_raw, config.msg_length_width, width)
print(in_data)
print(r_samples)
print(r_packets)
self.assertEqual(len(in_data), len(r_samples))
for e, r in zip(in_data, r_samples):
self.assertEqual(e, r)
e_even = [s for s in in_data if s%2==0]
r_even = [p[1] for p in r_packets]
self.assertEqual(len(e_even), len(r_even))
for e, r in zip(e_even, r_even):
self.assertEqual(e, r)
def test_one(self):
packet = [2159820100L, 878477756, pow(2, 23)+1, 2, 3, 4]
packets = [packet]*10
data = range(1, 100)
for packet in packets:
data.extend(packet)
data.extend(range(100, 110))
buffer_length = 128
defines = config.updated_defines(
{'COMBINER_BUFFER_LENGTH': buffer_length,
'LOG_COMBINER_BUFFER_LENGTH': logceil(buffer_length),
'MAX_PACKET_LENGTH': pow(2, config.msg_length_width),
})
executable = buildutils.generate_icarus_executable(
'message', 'message_stream_combiner_one', '-72', defines=defines)
fpgaimage = buildutils.generate_B100_image(
'message', 'message_stream_combiner_one', '-72', defines=defines)
tb_icarus = TestBenchIcarusOuter(executable, in_raw=data)
tb_b100 = TestBenchB100(fpgaimage, in_raw=data)
for tb, steps in (
(tb_icarus, 10000),
(tb_b100, 100000),
):
tb.run(steps)
self.assertEqual(len(data), len(tb.out_raw))
for e, r in zip(data, tb.out_raw):
self.assertEqual(e, r)
def test_one(self):
"""
Test the dit_series module.
"""
width = config.default_width
sendnth = config.default_sendnth
# Changing N will require resynthesis.
N = 16
# Arguments used for producing verilog from templates.
extraargs = {'N': N,
'width': width}
# Amount of data to send.
n_data = 1*N
# Define the input.
# I think must have abs mag 1 so divide by sqrt(2)
in_samples = [random.random()*2-1 + random.random()*2j-1j for i in range(n_data)]
factor = pow(2, -0.5)
in_samples = [s*factor for s in in_samples]
steps_rqd = len(in_samples)*sendnth + 100
# Define meta data
mwidth = 3
in_ms = [random.randint(0, pow(2,mwidth)-1) for d in in_samples]
steps_rqd = n_data * sendnth * 2 + 1000
# Calculate expected output
e_samples = []
for stage_samples in [in_samples[i*N:(i+1)*N] for i in range(n_data/N)]:
e_samples.extend(fft.fft(stage_samples))
e_samples = [s/N for s in e_samples]
# Create, setup and simulate the test bench.
defines = config.updated_defines(
{'WIDTH': width,
'MWIDTH': mwidth,
'N': N,
})
executable_inner = buildutils.generate_icarus_executable(
'fft', 'dit_series_inner', '-{0}'.format(N), defines=defines,
extraargs=extraargs)
#executable_outer = buildutils.generate_icarus_executable(
# 'fft', 'dit_series', '-{0}'.format(N), defines=defines,
# extraargs=extraargs)
#fpgaimage = buildutils.generate_B100_image(
# 'fft', 'stage_to_stage', '-{0}'.format(N), defines=defines,
# extraargs=extraargs)
tb_icarus_inner = TestBenchIcarusInner(executable_inner, in_samples, in_ms)
#tb_icarus_outer = TestBenchIcarusOuter(executable_outer, in_samples)
#tb_b100 = TestBenchB100(fpgaimage, in_samples)
for tb, steps, check_ms in (
(tb_icarus_inner, steps_rqd, True),
#(tb_icarus_outer, steps_rqd, False),
#(tb_b100, 100000, False),
):
tb.run(steps)
# Confirm that our data is correct.
self.assertEqual(len(tb.out_samples), len(e_samples))
for r, e in zip(tb.out_samples, e_samples):
self.assertAlmostEqual(e, r, 3)
if check_ms:
self.assertEqual(len(tb.out_ms), len(in_ms))
for r, e in zip(tb.out_ms, in_ms):
self.assertEqual(e, r)
def test_one_stream(self):
"""
Test the stream combiner with a single stream of data.
"""
width = 32
sendnth = 4
input_buffer_length = 64
max_packet_length = 1024
# First bit is 0 so data is from 0 to pow(2, 31)-1
maxint = pow(2, width-1)-1
n_data = 10
data = [self.rg.randint(0, maxint) for d in range(n_data)]
# How many steps are required to simulate the data.
steps_rqd = n_data * sendnth * 2 + 1000
# Create, setup and simulate the test bench.
defines = config.updated_defines(
{'N_STREAMS': 1,
'LOG_N_STREAMS': 1,
'WIDTH': width,
'INPUT_BUFFER_LENGTH': 16,
'LOG_INPUT_BUFFER_LENGTH': 4,
'MAX_PACKET_LENGTH': 16,
'LOG_MAX_PACKET_LENGTH': 4,
})
executable = buildutils.generate_icarus_executable(
'message', 'message_stream_combiner', '-one_stream', defines)
tb = TestBenchIcarusOuter(executable, in_raw=data, width=width,
output_msgs=False)
tb.run(steps_rqd)
# Confirm that our data is correct.
self.assertEqual(len(tb.out_raw), len(data))
for r, e in zip(tb.out_raw, data):
self.assertEqual(e, r)
def test_one(self):
packet = [2159820100L, 878477756, pow(2, 23) + 1, 2, 3, 4]
packets = [packet] * 10
data = range(1, 100)
for packet in packets:
data.extend(packet)
data.extend(range(100, 110))
buffer_length = 128
defines = config.updated_defines({
'COMBINER_BUFFER_LENGTH':
buffer_length,
'LOG_COMBINER_BUFFER_LENGTH':
logceil(buffer_length),
'MAX_PACKET_LENGTH':
pow(2, config.msg_length_width),
})
executable = buildutils.generate_icarus_executable(
'message', 'message_stream_combiner_one', '-72', defines=defines)
fpgaimage = buildutils.generate_B100_image(
'message', 'message_stream_combiner_one', '-72', defines=defines)
tb_icarus = TestBenchIcarusOuter(executable, in_raw=data)
tb_b100 = TestBenchB100(fpgaimage, in_raw=data)
for tb, steps in (
(tb_icarus, 10000),
(tb_b100, 100000),
):
tb.run(steps)
self.assertEqual(len(data), len(tb.out_raw))
for e, r in zip(data, tb.out_raw):
self.assertEqual(e, r)
def test_one_stream(self):
"""
Test the stream combiner with a single stream of data.
"""
width = 32
sendnth = 4
input_buffer_length = 64
max_packet_length = 1024
# First bit is 0 so data is from 0 to pow(2, 31)-1
maxint = pow(2, width - 1) - 1
n_data = 10
data = [self.rg.randint(0, maxint) for d in range(n_data)]
# How many steps are required to simulate the data.
steps_rqd = n_data * sendnth * 2 + 1000
# Create, setup and simulate the test bench.
defines = config.updated_defines({
'N_STREAMS': 1,
'LOG_N_STREAMS': 1,
'WIDTH': width,
'INPUT_BUFFER_LENGTH': 16,
'LOG_INPUT_BUFFER_LENGTH': 4,
'MAX_PACKET_LENGTH': 16,
'LOG_MAX_PACKET_LENGTH': 4,
})
executable = buildutils.generate_icarus_executable(
'message', 'message_stream_combiner', '-one_stream', defines)
tb = TestBenchIcarusOuter(executable,
in_raw=data,
width=width,
output_msgs=False)
tb.run(steps_rqd)
# Confirm that our data is correct.
self.assertEqual(len(tb.out_raw), len(data))
for r, e in zip(tb.out_raw, data):
self.assertEqual(e, r)
def test_one(self):
"""
Tests split module and message stream combiner together.
"""
width = 32
sendnth = 2
max_packet_length = 10
n_packets = 20
data1 = []
for i in range(n_packets):
length = random.randint(0, max_packet_length)
packet = msg_utils.generate_random_packet(length, config.msg_length_width,
width)
data1.extend(packet)
max_val = pow(2, width-1)-1
data2 = [random.randint(1, max_val) for i in range(len(data1))]
i_data = []
for d1, d2 in zip(data1, data2):
i_data.append(d1)
i_data.append(d2)
a_data = data1 + data2
padded_data = i_data + [0]*1000
buffer_length = 128
defines = config.updated_defines(
{'COMBINER_BUFFER_LENGTH': buffer_length,
'LOG_COMBINER_BUFFER_LENGTH': logceil(buffer_length),
'MAX_PACKET_LENGTH': pow(2, config.msg_length_width),
'ERRORCODE': 666,
'WIDTH': width,
})
executable = buildutils.generate_icarus_executable(
'message', 'splitcombiner', '-test', defines=defines)
fpgaimage = buildutils.generate_B100_image(
'message', 'splitcombiner', '-test', defines=defines)
tb_icarus = TestBenchIcarusOuter(executable, in_raw=i_data,
sendnth=sendnth)
tb_b100 = TestBenchB100(fpgaimage, in_raw=padded_data)
for tb, steps in (
(tb_icarus, len(i_data)*sendnth*2+1000),
(tb_b100, 100000),
):
tb.run(steps)
e_samples, e_packets = msg_utils.stream_to_samples_and_packets(
a_data, config.msg_length_width, width)
r_samples, r_packets = msg_utils.stream_to_samples_and_packets(
tb.out_raw, config.msg_length_width, width)
# Remove 0's from samples.
# The splitter can introduce 0's at beginning and end.
r_samples = [r for r in r_samples if r != 0]
self.assertEqual(len(e_samples), len(r_samples))
for e, r in zip(e_samples, r_samples):
self.assertEqual(e, r)
# Confirm all the packets are equal.
self.assertEqual(len(e_packets), len(r_packets))
for ep, rp in zip(e_packets, r_packets):
self.assertEqual(len(ep), len(rp))
for e, r in zip(ep, rp):
self.assertEqual(e, r)
def setUp(self):
# Number of channels
self.M = 4
self.logM = int(math.log(self.M) / math.log(2))
# The amount of data to send
self.n_data = self.M * 30 #200
# Baseband sampling rate
self.fs = 1000
# Input samp rate to channelizer
self.ifs = self.M * self.fs
# Each channel contains a pure frequency with an offset and
# amplitude.
self.freqs = [0, 100, 200, -300]
self.amplitudes = [1, 1, -0.2, 0.5]
# Random number generator
rg = random.Random(0)
self.myrand = rg.random
self.myrandint = rg.randint
# Width of a complex number
self.width = 32
# Generate some taps
self.taps, self.tapscale = get_channelizer_taps(self.M, n_taps=100)
# How often to send input.
# For large FFTs this must be larger since the speed scales as MlogM.
# Otherwise we get an overflow error.
self.sendnth = 8
# Get the input data
self.data = get_mixed_sinusoids(self.fs, self.n_data, self.freqs,
self.amplitudes)
# Scale the input data to remain in (-1 to 1)
datamax = 0
for d in self.data:
datamax = max(datamax, abs(d.real), abs(d.imag))
self.inputscale = datamax
self.data = [d / datamax for d in self.data]
# Send in some meta data
self.mwidth = 3
self.ms = [self.myrandint(0, 7) for d in self.data]
# Create the test bench
name = 'complex'
defines = config.updated_defines({
"DEBUG": False,
"WIDTH": self.width,
"MWIDTH": self.mwidth
})
rtaps = []
for tt in self.taps:
rtaps.append(list(reversed(tt)))
self.tb = ChannelizerTestBenchIcarus(name, self.M, rtaps, self.data,
self.sendnth, self.ms, defines)
self.ftb = FilterbankTestBenchIcarus(name, self.M, len(self.taps[0]),
self.taps, self.data,
self.sendnth, self.ms, defines)
self.ftb.prepare()
self.tb.prepare()
def test_combo(self):
"""
Tests sample msg splitter and message stream combiner together.
"""
top_packet_length = 64
n_packets = 20
width = 32
prob_start = 0.1
data, packets = msg_utils.generate_random_packets(
top_packet_length,
n_packets,
config.msg_length_width,
width,
prob_start,
self.rg,
none_sample=False)
padded_data = data
buffer_length = 128
defines = config.updated_defines({
'COMBINER_BUFFER_LENGTH':
buffer_length,
'LOG_COMBINER_BUFFER_LENGTH':
logceil(buffer_length),
'MAX_PACKET_LENGTH':
pow(2, config.msg_length_width),
})
executable = buildutils.generate_icarus_executable('message',
'combo',
'-test',
defines=defines)
fpgaimage = buildutils.generate_B100_image('message',
'combo',
'-test',
defines=defines)
tb_icarus = TestBenchIcarusOuter(executable, in_raw=data)
tb_b100 = TestBenchB100(fpgaimage, in_raw=padded_data)
for tb, steps in (
(tb_icarus, 10000),
(tb_b100, 100000),
):
tb.run(steps)
e_samples, e_packets = msg_utils.stream_to_samples_and_packets(
data, config.msg_length_width, width)
r_samples, r_packets = msg_utils.stream_to_samples_and_packets(
tb.out_raw, config.msg_length_width, width)
# Confirm all the samples are equal.
self.assertEqual(len(e_samples), len(r_samples))
for e, r in zip(e_samples, r_samples):
self.assertEqual(e, r)
# Confirm all the packets are equal.
self.assertEqual(len(e_packets), len(r_packets))
for ep, rp in zip(e_packets, r_packets):
self.assertEqual(len(ep), len(rp))
for e, r in zip(ep, rp):
self.assertEqual(e, r)
def test_one(self):
"""
Test the stage module.
"""
width = config.default_width
sendnth = config.default_sendnth
# Changing N will require resynthesis.
N = 8
# Arguments used for producing verilog from templates.
extraargs = {}
# Amount of data to send.
n_data = 2*N
# Define the input
in_samples = [random.random()*2-1 + random.random()*2j-1j for i in range(n_data)]
steps_rqd = len(in_samples)*sendnth + 100
# Define meta data
mwidth = 3
in_ms = [random.randint(0, pow(2,mwidth)-1) for d in in_samples]
expected = in_samples
steps_rqd = n_data * sendnth * 2 + 1000
# Create, setup and simulate the test bench.
defines = config.updated_defines(
{'WIDTH': width,
'MWIDTH': mwidth,
'N': N
})
executable_inner = buildutils.generate_icarus_executable(
'fft', 'stage_inner', '-{0}'.format(N), defines=defines,
extraargs=extraargs)
executable_outer = buildutils.generate_icarus_executable(
'fft', 'stage', '-{0}'.format(N), defines=defines,
extraargs=extraargs)
#fpgaimage = buildutils.generate_B100_image(
# 'fft', 'stage', '-{0}'.format(N), defines=defines,
# extraargs=extraargs)
tb_icarus_inner = TestBenchIcarusInner(executable_inner, in_samples, in_ms)
tb_icarus_outer = TestBenchIcarusOuter(executable_outer, in_samples)
#tb_b100 = TestBenchB100(fpgaimage, in_samples)
for tb, steps, check_ms in (
(tb_icarus_inner, steps_rqd, True),
(tb_icarus_outer, steps_rqd, False),
#(tb_b100, 100000, False),
):
tb.run(steps)
# Confirm that our data is correct.
self.assertEqual(len(tb.out_samples), len(expected))
for r, e in zip(tb.out_samples, expected):
self.assertAlmostEqual(e, r, 3)
if check_ms:
self.assertEqual(len(tb.out_ms), len(in_ms))
for r, e in zip(tb.out_ms, in_ms):
self.assertEqual(e, r)
def test_bits(self):
"""
Tests the bits qa_wrapper.
"""
width=32
sendnth = 70
max_sample = pow(2, width)-1
n_samples = 2
data = [self.rg.randint(1, max_sample) for i in range(n_samples)]
defines = config.updated_defines(
{
'LOG_WIDTH': logceil(width),
'ERRORCODE': 666,
'WIDTH': width,
'LOG_SENDNTH': 12,
})
executable = buildutils.generate_icarus_executable(
'uhd', 'bits', '-test', defines=defines)
fpgaimage = buildutils.generate_B100_image(
'uhd', 'bits', '-test', defines=defines)
tb_icarus = TestBenchIcarusOuter(executable, in_raw=data, sendnth=sendnth)
tb_b100 = TestBenchB100(fpgaimage, in_raw=data)
for tb, steps in (
(tb_icarus, 5000),
(tb_b100, 100000),
):
tb.run(steps)
start_pos = None
for i, x in enumerate(tb.out_raw):
if (x==width-1):
start_pos = i
break
for i, x in reversed(zip(range(0, len(tb.out_raw)), tb.out_raw)):
if (x==width-1):
stop_pos = i
break
if start_pos is None:
raise ValueError("{0} not found in output".format(width-1))
out = tb.out_raw[start_pos: stop_pos + 2*width]
bitted = [out[i*2*width+1:(i+1)*2*width+1:2] for i in range(len(out)/width/2)]
poses = [out[i*2*width:(i+1)*2*width:2] for i in range(len(out)/width/2)]
expected = [31-x for x in range(32)]
for i, p in enumerate(poses):
if (p != expected):
print(i)
print(p)
self.assertEqual(p, expected)
r_ints = [bits_to_int(bits) for bits in bitted]
r_ints = [x for x in r_ints if x != 0]
self.assertEqual(len(data), len(r_ints))
for e, r in zip(data, r_ints):
self.assertEqual(e, r)
def random_template(self, nlog2, width, N_data_sets, sendnth):
"""
Test the DUT with a random complex stream.
"""
N = pow(2, nlog2)
# Approx many steps we'll need.
steps_rqd = 2 * N_data_sets * int(40.0 / 8 / 3 * nlog2 * N)
# Generate some random input.
data_sets = []
data = []
for i in range(0, N_data_sets):
nd = [
self.myrand() * 2 - 1 + self.myrand() * 2j - 1j
for x in range(N)
]
data_sets.append(nd)
data += nd
mwidth = 3
ms = [self.myrandint(0, pow(2, mwidth) - 1) for d in data]
# Create, setup and simulate the test bench.
defines = config.updated_defines({
"DEBUG": False,
"WIDTH": width,
"MWIDTH": mwidth
})
tb = DITTestBenchIcarus('standard',
N,
data,
sendnth,
ms,
defines=defines)
tb.prepare()
tb.run(steps_rqd)
# Confirm that our data is correct.
self.assertEqual(len(tb.out_samples), len(data))
rffts = [tb.out_samples[N * i:N * (i + 1)] for i in range(N_data_sets)]
# Compare the FFT to that generated by numpy
# The FFT from our DUT is divided by N to prevent overflow so we do the
# same to the numpy output.
effts = [[x / N for x in fft.fft(data_set)] for data_set in data_sets]
i = 0
self.assertEqual(len(rffts), len(effts))
max_delta = 0.02
for rfft, efft in zip(rffts, effts):
self.assertEqual(len(rfft), len(efft))
for e, r in zip(efft, rfft):
delta = abs(r - e)
self.assertTrue(delta < max_delta)
# Compare ms
for r, e in zip(tb.out_ms, ms):
self.assertEqual(r, e)
def test_one(self):
"""
Test the filter module.
"""
width = config.default_width
sendnth = config.default_sendnth
# Changing filter_length will require resynthesis.
filter_length = 4
taps = [random.random()*2-1 for i in range(filter_length)]
total = sum([abs(t) for t in taps])
taps = [t/total for t in taps]
# Arguments used for producing verilog from templates.
extraargs = {'summult_length': filter_length,}
# Amount of data to send.
n_data = 10
# Define the input
in_samples = [random.random()*2-1 + random.random()*2j-1j for i in range(n_data)]
in_samples += [0]*(filter_length-1)
steps_rqd = len(in_samples)*sendnth + 100
# Define meta data
mwidth = 1
in_ms = [random.randint(0, pow(2,mwidth)-1) for d in in_samples]
expected = convolve(in_samples, taps)
steps_rqd = n_data * sendnth * 2 + 1000
filter_id = 123
# Create, setup and simulate the test bench.
defines = config.updated_defines(
{'WIDTH': width,
'FILTER_LENGTH': filter_length,
'FILTER_ID': filter_id,
})
executable_inner = buildutils.generate_icarus_executable(
'flter', 'filter_inner', '-test', defines=defines, extraargs=extraargs)
executable_outer = buildutils.generate_icarus_executable(
'flter', 'filter', '-test', defines=defines, extraargs=extraargs)
fpgaimage = buildutils.generate_B100_image(
'flter', 'filter', '-test', defines=defines,
extraargs=extraargs)
start_msgs = taps_to_start_msgs(taps, defines['WIDTH']/2, filter_id)
tb_icarus_inner = TestBenchIcarusInner(executable_inner, in_samples, in_ms, start_msgs)
tb_icarus_outer = TestBenchIcarusOuter(executable_outer, in_samples, start_msgs)
tb_b100 = TestBenchB100(fpgaimage, in_samples, start_msgs)
for tb, steps in (
(tb_icarus_inner, steps_rqd),
(tb_icarus_outer, steps_rqd),
(tb_b100, 100000),
):
tb.run(steps)
# Confirm that our data is correct.
self.assertEqual(len(tb.out_samples), len(expected))
for r, e in zip(tb.out_samples, expected):
self.assertAlmostEqual(e, r, 3)
def setUp(self):
# Number of channels
self.M = 4
self.logM = int(math.log(self.M)/math.log(2))
# The amount of data to send
self.n_data = self.M * 30#200
# Baseband sampling rate
self.fs = 1000
# Input samp rate to channelizer
self.ifs = self.M*self.fs
# Each channel contains a pure frequency with an offset and
# amplitude.
self.freqs = [0, 100, 200, -300]
self.amplitudes = [1, 1, -0.2, 0.5]
# Random number generator
rg = random.Random(0)
self.myrand = rg.random
self.myrandint = rg.randint
# Width of a complex number
self.width = 32
# Generate some taps
self.taps, self.tapscale = get_channelizer_taps(self.M, n_taps=100)
# How often to send input.
# For large FFTs this must be larger since the speed scales as MlogM.
# Otherwise we get an overflow error.
self.sendnth = 8
# Get the input data
self.data = get_mixed_sinusoids(self.fs, self.n_data, self.freqs, self.amplitudes)
# Scale the input data to remain in (-1 to 1)
datamax = 0
for d in self.data:
datamax = max(datamax, abs(d.real), abs(d.imag))
self.inputscale = datamax
self.data = [d/datamax for d in self.data]
# Send in some meta data
self.mwidth = 3
self.ms = [self.myrandint(0, 7) for d in self.data]
# Create the test bench
name = 'complex'
defines = config.updated_defines({"DEBUG": False,
"WIDTH": self.width,
"MWIDTH": self.mwidth})
rtaps = []
for tt in self.taps:
rtaps.append(list(reversed(tt)))
self.tb = ChannelizerTestBenchIcarus(name, self.M, rtaps, self.data,
self.sendnth, self.ms, defines)
self.ftb = FilterbankTestBenchIcarus(name, self.M, len(self.taps[0]), self.taps, self.data,
self.sendnth, self.ms, defines)
self.ftb.prepare()
self.tb.prepare()
def test_bits(self):
width = 32
maxint = pow(2, width)-1
n_data = 10
data = [random.randint(1, maxint) for d in range(n_data)]
buffer_length = 128
defines = config.updated_defines(
{'COMBINER_BUFFER_LENGTH': buffer_length,
'LOG_COMBINER_BUFFER_LENGTH': logceil(buffer_length),
'MAX_PACKET_LENGTH': pow(2, config.msg_length_width),
'WIDTH': width,
'LOG_SENDNTH': 14,
'LOG_WIDTH': logceil(width),
'ERRORCODE': 666,
})
executable = buildutils.generate_icarus_executable(
'message', 'message_stream_combiner_bits', '-test', defines=defines)
fpgaimage = buildutils.generate_B100_image(
'message', 'message_stream_combiner_bits', '-test', defines=defines)
tb_icarus = TestBenchIcarusOuter(executable, in_raw=data, sendnth=70)
tb_b100 = TestBenchB100(fpgaimage, in_raw=data)
for tb, steps in (
(tb_icarus, 10000),
(tb_b100, 100000),
):
tb.run(steps)
start_pos = None
for i, x in enumerate(tb.out_raw):
if (x==width-1):
start_pos = i
break
for i, x in reversed(zip(range(0, len(tb.out_raw)), tb.out_raw)):
if (x==width-1):
stop_pos = i
break
if start_pos is None:
raise ValueError("{0} not found in output".format(width-1))
out = tb.out_raw[start_pos: stop_pos + 2*width]
bitted = [out[i*2*width+1:(i+1)*2*width+1:2] for i in range(len(out)/width/2)]
poses = [out[i*2*width:(i+1)*2*width:2] for i in range(len(out)/width/2)]
expected = [31-x for x in range(32)]
for i, p in enumerate(poses):
self.assertEqual(p, expected)
r_ints = [bits_to_int(bits) for bits in bitted]
r_ints = [x for x in r_ints if x != 0]
self.assertEqual(len(data), len(r_ints))
for e, r in zip(data, r_ints):
self.assertEqual(e, r)
def test_slicer(self):
"""
Test the stream slicer.
"""
width = 32
n_slices = 3
sendnth = 4
buffer_length = 16
n_data = 10
data = []
expected_data = []
mfactor = pow(2, width)
for i in range(n_data):
m = pow(mfactor, n_slices - 1)
t = 0
for s in range(n_slices):
d = self.rg.randint(0, mfactor - 1)
t += d * m
m = m / mfactor
expected_data.append(d)
data.append(t)
# How many steps are required to simulate the data.
steps_rqd = len(data) * sendnth * 2 #+ 1000
# Create, setup and simulate the test bench.
defines = config.updated_defines({
'N_SLICES':
3,
'LOG_N_SLICES':
logceil(n_slices),
'WIDTH':
width,
'BUFFER_LENGTH':
buffer_length,
'LOG_BUFFER_LENGTH':
logceil(buffer_length),
})
executable = buildutils.generate_icarus_executable(
'message', 'message_slicer', '-test', defines)
tb = TestBenchIcarusOuter(executable,
in_raw=data,
width=width,
output_msgs=False)
tb.run(steps_rqd)
# Now check output
self.assertEqual(len(expected_data), len(tb.out_raw))
for e, r in zip(expected_data, tb.out_raw):
self.assertAlmostEqual(e, r, 3)
def test_one(self):
"""
Test the buffer_AA and buffer_BB module.
"""
width = config.default_width
sendnth = 1
maxint = pow(2, width)-1
buffer_length = 32
n_data = 100
data = [random.randint(1, maxint) for d in range(n_data)]
# How many steps are required to simulate the data.
steps_rqd = n_data * sendnth * 2 + 1000
# Create, setup and simulate the test bench.
defines = config.updated_defines(
{'WIDTH': width,
'BUFFER_LENGTH': buffer_length,
'LOG_BUFFER_LENGTH': logceil(buffer_length),
'WRITEERRORCODE': 666,
'READERRORCODE': 777,
})
executableAA = buildutils.generate_icarus_executable(
'flow', 'buffer_AA', '-test', defines=defines)
fpgaimageAA = buildutils.generate_B100_image(
'flow', 'buffer_AA', '-test', defines=defines)
executableBB = buildutils.generate_icarus_executable(
'flow', 'buffer_BB', '-test', defines=defines)
fpgaimageBB = buildutils.generate_B100_image(
'flow', 'buffer_BB', '-test', defines=defines)
tb_icarusAA = TestBenchIcarusOuter(executableAA, in_raw=data,
output_msgs=False)
tb_b100AA = TestBenchB100(fpgaimageAA, in_raw=data, output_msgs=False)
tb_icarusBB = TestBenchIcarusOuter(executableBB, in_raw=data,
output_msgs=False)
tb_b100BB = TestBenchB100(fpgaimageBB, in_raw=data, output_msgs=False)
for tb, steps in (
(tb_icarusAA, steps_rqd),
(tb_b100AA, 100000),
(tb_icarusBB, steps_rqd),
(tb_b100BB, 100000),
):
tb.run(steps)
# Confirm that our data is correct.
stream = None
self.assertEqual(len(tb.out_raw), len(data))
for r, e in zip(tb.out_raw, data):
self.assertEqual(e, r)
def test_return_one(self):
"""
Test the split module.
"""
width = config.default_width
sendnth = 4
maxint = pow(2, width)-1
n_data = 100
n_streams = 2
data = [random.randint(0, maxint) for d in range(n_data)]
# Work out what the expected result is.
# We don't know which stream will be returned.
expected_data = data[::2]
alt_expected_data = data[1::2]
# How many steps are required to simulate the data.
steps_rqd = n_data * sendnth * 2 + 1000
# Create, setup and simulate the test bench.
defines = config.updated_defines(
{'WIDTH': width,
})
executable = buildutils.generate_icarus_executable(
'flow', 'split_return_one', '-test', defines=defines)
fpgaimage = buildutils.generate_B100_image(
'flow', 'split_return_one', '-test', defines=defines)
tb_icarus = TestBenchIcarusOuter(executable, in_raw=data,
output_msgs=False)
tb_b100 = TestBenchB100(fpgaimage, in_raw=data, output_msgs=False)
for tb, steps in (
(tb_icarus, steps_rqd),
(tb_b100, 100000),
):
tb.run(steps)
# Confirm that our data is correct.
stream = None
self.assertEqual(len(tb.out_raw), len(expected_data))
for r, e, a in zip(tb.out_raw, expected_data, alt_expected_data):
if stream is None:
if (r != e):
stream = 2
else:
stream = 1
if stream == 1:
self.assertEqual(e, r)
else:
self.assertEqual(a, r)
def test_combo(self):
"""
Tests sample msg splitter and message stream combiner together.
"""
top_packet_length = 64
n_packets = 20
width = 32
prob_start = 0.1
data, packets = msg_utils.generate_random_packets(
top_packet_length, n_packets, config.msg_length_width,
width, prob_start, self.rg, none_sample=False)
padded_data = data
buffer_length = 128
defines = config.updated_defines(
{'COMBINER_BUFFER_LENGTH': buffer_length,
'LOG_COMBINER_BUFFER_LENGTH': logceil(buffer_length),
'MAX_PACKET_LENGTH': pow(2, config.msg_length_width),
})
executable = buildutils.generate_icarus_executable(
'message', 'combo', '-test', defines=defines)
fpgaimage = buildutils.generate_B100_image(
'message', 'combo', '-test', defines=defines)
tb_icarus = TestBenchIcarusOuter(executable, in_raw=data)
tb_b100 = TestBenchB100(fpgaimage, in_raw=padded_data)
for tb, steps in (
(tb_icarus, 10000),
(tb_b100, 100000),
):
tb.run(steps)
e_samples, e_packets = msg_utils.stream_to_samples_and_packets(
data, config.msg_length_width, width)
r_samples, r_packets = msg_utils.stream_to_samples_and_packets(
tb.out_raw, config.msg_length_width, width)
# Confirm all the samples are equal.
self.assertEqual(len(e_samples), len(r_samples))
for e, r in zip(e_samples, r_samples):
self.assertEqual(e, r)
# Confirm all the packets are equal.
self.assertEqual(len(e_packets), len(r_packets))
for ep, rp in zip(e_packets, r_packets):
self.assertEqual(len(ep), len(rp))
for e, r in zip(ep, rp):
self.assertEqual(e, r)
def random_template(self, nlog2, width, N_data_sets, sendnth):
"""
Test the DUT with a random complex stream.
"""
N = pow(2, nlog2)
# Approx many steps we'll need.
steps_rqd = 2*N_data_sets*int(40.0 / 8 / 3 * nlog2 * N)
# Generate some random input.
data_sets = []
data = []
for i in range(0, N_data_sets):
nd = [self.myrand()*2-1 + self.myrand()*2j-1jfor x in range(N)]
data_sets.append(nd)
data += nd
mwidth = 3
ms = [self.myrandint(0, pow(2, mwidth)-1) for d in data]
# Create, setup and simulate the test bench.
defines = config.updated_defines({"DEBUG": False,
"WIDTH": width,
"MWIDTH": mwidth})
tb = DITTestBenchIcarus('standard', N, data, sendnth, ms, defines=defines)
tb.prepare()
tb.run(steps_rqd)
# Confirm that our data is correct.
self.assertEqual(len(tb.out_samples), len(data))
rffts = [tb.out_samples[N*i: N*(i+1)] for i in range(N_data_sets)]
# Compare the FFT to that generated by numpy
# The FFT from our DUT is divided by N to prevent overflow so we do the
# same to the numpy output.
effts = [[x/N for x in fft.fft(data_set)] for data_set in data_sets]
i = 0
self.assertEqual(len(rffts), len(effts))
max_delta = 0.02
for rfft, efft in zip(rffts, effts):
self.assertEqual(len(rfft), len(efft))
for e,r in zip(efft, rfft):
delta = abs(r-e)
self.assertTrue(delta < max_delta)
# Compare ms
for r, e in zip(tb.out_ms, ms):
self.assertEqual(r, e)
def test_slicer(self):
"""
Test the stream slicer.
"""
width = 32
n_slices = 3
sendnth = 4
buffer_length = 16
n_data = 10
data = []
expected_data = []
mfactor = pow(2, width)
for i in range(n_data):
m = pow(mfactor, n_slices-1)
t = 0
for s in range(n_slices):
d = self.rg.randint(0, mfactor-1)
t += d * m
m = m / mfactor
expected_data.append(d)
data.append(t)
# How many steps are required to simulate the data.
steps_rqd = len(data) * sendnth * 2 #+ 1000
# Create, setup and simulate the test bench.
defines = config.updated_defines(
{'N_SLICES': 3,
'LOG_N_SLICES': logceil(n_slices),
'WIDTH': width,
'BUFFER_LENGTH': buffer_length,
'LOG_BUFFER_LENGTH': logceil(buffer_length),
})
executable = buildutils.generate_icarus_executable(
'message', 'message_slicer', '-test', defines)
tb = TestBenchIcarusOuter(executable, in_raw=data, width=width,
output_msgs=False)
tb.run(steps_rqd)
# Now check output
self.assertEqual(len(expected_data), len(tb.out_raw))
for e,r in zip(expected_data, tb.out_raw):
self.assertAlmostEqual(e, r, 3)
def test_one(self):
"""
Tests passing debug messages back.
"""
width = 32
sendnth = 2
max_val = pow(2, width - 2) - 1
n_data = 10
in_data = [random.randint(1, max_val) for i in range(n_data)]
defines = config.updated_defines({})
executable = buildutils.generate_icarus_executable('message',
'debug',
'-test',
defines=defines)
fpgaimage = buildutils.generate_B100_image('message',
'debug',
'-test',
defines=defines)
tb_icarus = TestBenchIcarusOuter(executable,
in_raw=in_data,
sendnth=sendnth)
tb_b100 = TestBenchB100(fpgaimage, in_raw=in_data)
for tb, steps in (
#(tb_icarus, len(in_data)*sendnth*2+1000),
(tb_b100, 100000), ):
tb.run(steps)
r_samples, r_packets = msg_utils.stream_to_samples_and_packets(
tb.out_raw, config.msg_length_width, width)
print(in_data)
print(r_samples)
print(r_packets)
self.assertEqual(len(in_data), len(r_samples))
for e, r in zip(in_data, r_samples):
self.assertEqual(e, r)
e_even = [s for s in in_data if s % 2 == 0]
r_even = [p[1] for p in r_packets]
self.assertEqual(len(e_even), len(r_even))
for e, r in zip(e_even, r_even):
self.assertEqual(e, r)
def test_one(self):
"""
Test the split module.
"""
width = 32
sendnth = 4
maxint = pow(2, width)-1
n_data = 100
n_streams = 3
data = [random.randint(0, maxint) for d in range(n_data)]
# Work out what the expected result is.
expected_data = []
for ds in [data[n_streams*i:n_streams*(i+1)] for i in range(n_data/n_streams)]:
e_d = 0
f = 1
for d in ds:
e_d += d*f
f *= pow(2, width)
expected_data.append(e_d)
# How many steps are required to simulate the data.
steps_rqd = n_data * sendnth * 2 + 1000
# Create, setup and simulate the test bench.
defines = config.updated_defines(
{'N_OUT_STREAMS': n_streams,
'LOG_N_OUT_STREAMS': logceil(n_streams),
'WIDTH': width,
})
executable = buildutils.generate_icarus_executable(
'flow', 'split', '-test', defines)
tb = TestBenchIcarusOuter(executable, in_raw=data, width=width,
output_msgs=False)
tb.run(steps_rqd)
# Confirm that our data is correct.
self.assertEqual(len(tb.out_raw), len(expected_data))
for r, e in zip(tb.out_raw, expected_data):
self.assertEqual(e, r)
def test_one(self):
"""
Test the dit_series module.
"""
width = config.default_width
sendnth = config.default_sendnth
# Changing N will require resynthesis.
N = 16
# Arguments used for producing verilog from templates.
extraargs = {'N': N, 'width': width}
# Amount of data to send.
n_data = 1 * N
# Define the input.
# I think must have abs mag 1 so divide by sqrt(2)
in_samples = [
random.random() * 2 - 1 + random.random() * 2j - 1j
for i in range(n_data)
]
factor = pow(2, -0.5)
in_samples = [s * factor for s in in_samples]
steps_rqd = len(in_samples) * sendnth + 100
# Define meta data
mwidth = 3
in_ms = [random.randint(0, pow(2, mwidth) - 1) for d in in_samples]
steps_rqd = n_data * sendnth * 2 + 1000
# Calculate expected output
e_samples = []
for stage_samples in [
in_samples[i * N:(i + 1) * N] for i in range(n_data / N)
]:
e_samples.extend(fft.fft(stage_samples))
e_samples = [s / N for s in e_samples]
# Create, setup and simulate the test bench.
defines = config.updated_defines({
'WIDTH': width,
'MWIDTH': mwidth,
'N': N,
})
executable_inner = buildutils.generate_icarus_executable(
'fft',
'dit_series_inner',
'-{0}'.format(N),
defines=defines,
extraargs=extraargs)
#executable_outer = buildutils.generate_icarus_executable(
# 'fft', 'dit_series', '-{0}'.format(N), defines=defines,
# extraargs=extraargs)
#fpgaimage = buildutils.generate_B100_image(
# 'fft', 'stage_to_stage', '-{0}'.format(N), defines=defines,
# extraargs=extraargs)
tb_icarus_inner = TestBenchIcarusInner(executable_inner, in_samples,
in_ms)
#tb_icarus_outer = TestBenchIcarusOuter(executable_outer, in_samples)
#tb_b100 = TestBenchB100(fpgaimage, in_samples)
for tb, steps, check_ms in (
(tb_icarus_inner, steps_rqd, True),
#(tb_icarus_outer, steps_rqd, False),
#(tb_b100, 100000, False),
):
tb.run(steps)
# Confirm that our data is correct.
self.assertEqual(len(tb.out_samples), len(e_samples))
for r, e in zip(tb.out_samples, e_samples):
self.assertAlmostEqual(e, r, 3)
if check_ms:
self.assertEqual(len(tb.out_ms), len(in_ms))
for r, e in zip(tb.out_ms, in_ms):
self.assertEqual(e, r)
def test_bits(self):
width = 32
maxint = pow(2, width) - 1
n_data = 10
data = [random.randint(1, maxint) for d in range(n_data)]
buffer_length = 128
defines = config.updated_defines({
'COMBINER_BUFFER_LENGTH':
buffer_length,
'LOG_COMBINER_BUFFER_LENGTH':
logceil(buffer_length),
'MAX_PACKET_LENGTH':
pow(2, config.msg_length_width),
'WIDTH':
width,
'LOG_SENDNTH':
14,
'LOG_WIDTH':
logceil(width),
'ERRORCODE':
666,
})
executable = buildutils.generate_icarus_executable(
'message',
'message_stream_combiner_bits',
'-test',
defines=defines)
fpgaimage = buildutils.generate_B100_image(
'message',
'message_stream_combiner_bits',
'-test',
defines=defines)
tb_icarus = TestBenchIcarusOuter(executable, in_raw=data, sendnth=70)
tb_b100 = TestBenchB100(fpgaimage, in_raw=data)
for tb, steps in (
(tb_icarus, 10000),
(tb_b100, 100000),
):
tb.run(steps)
start_pos = None
for i, x in enumerate(tb.out_raw):
if (x == width - 1):
start_pos = i
break
for i, x in reversed(zip(range(0, len(tb.out_raw)), tb.out_raw)):
if (x == width - 1):
stop_pos = i
break
if start_pos is None:
raise ValueError("{0} not found in output".format(width - 1))
out = tb.out_raw[start_pos:stop_pos + 2 * width]
bitted = [
out[i * 2 * width + 1:(i + 1) * 2 * width + 1:2]
for i in range(len(out) / width / 2)
]
poses = [
out[i * 2 * width:(i + 1) * 2 * width:2]
for i in range(len(out) / width / 2)
]
expected = [31 - x for x in range(32)]
for i, p in enumerate(poses):
self.assertEqual(p, expected)
r_ints = [bits_to_int(bits) for bits in bitted]
r_ints = [x for x in r_ints if x != 0]
self.assertEqual(len(data), len(r_ints))
for e, r in zip(data, r_ints):
self.assertEqual(e, r)
def test_one(self):
"""
Test the butterfly module.
"""
sendnth = 5
n_data = 1
width = 32
in_samples = []
expected = []
xas = [random.random()*2-1 + random.random()*2j-1j for i in range(n_data)]
xbs = [random.random()*2-1 + random.random()*2j-1j for i in range(n_data)]
# Max val of w is 10000 (roughly 0.5)
ws = [0.5*(random.random()*2-1) + 0.5*(random.random()*2j-1j) for i in range(n_data)]
for xa, xb, w in zip(xas, xbs, ws):
in_samples.append(xa)
in_samples.append(xb)
in_samples.append(w)
ya = xa + xb*w
yb = xa - xb*w
expected.append(ya/2)
expected.append(yb/2)
steps_rqd = len(in_samples)*sendnth*2 + 100
# Define meta data
mwidth = 1
raw_ms = [random.randint(0, pow(2,mwidth)-1) for i in range(n_data)]
in_ms = []
expected_ms = []
for m in raw_ms:
in_ms.extend((m, 0, 0))
expected_ms.extend((m, 0))
defines = config.updated_defines({
'DEBUG': True,
})
executable_inner = buildutils.generate_icarus_executable(
'fft', 'butterfly_inner', '-test', defines=defines)
executable_outer = buildutils.generate_icarus_executable(
'fft', 'butterfly', '-test', defines=defines)
#fpgaimage = buildutils.generate_B100_image(
# 'fft', 'butterfly', '-test', defines=defines)
tb_icarus_inner = TestBenchIcarusInner(executable_inner, in_samples, in_ms, sendnth=sendnth)
tb_icarus_outer = TestBenchIcarusOuter(executable_outer, in_samples, sendnth=sendnth)
#tb_b100 = TestBenchB100(fpgaimage, in_samples)
for tb, steps, check_ms in (
(tb_icarus_inner, steps_rqd, True),
(tb_icarus_outer, steps_rqd, False),
#(tb_b100, 100000, False),
):
tb.run(steps)
# Confirm that our data is correct.
print(tb.out_raw)
print(tb.out_samples)
print(expected)
self.assertEqual(len(tb.out_samples), len(expected))
for msg in tb.out_messages:
print("message is")
print(msg)
xa = int_to_c(msg[1], width/2-1)
xbw = int_to_c(msg[2], width/2-1)
ya = int_to_c(msg[3], width/2-1)
yb = int_to_c(msg[4], width/2-1)
print("e xa is {0} xbw is {1}".format(xas[0]/2, xbs[0]*ws[0]/2))
print("r xa is {0} xbw is {1}".format(xa, xbw))
for r, e in zip(tb.out_samples, expected):
print(e, r)
self.assertAlmostEqual(e, r, 3)
if check_ms:
self.assertEqual(len(tb.out_ms), len(expected_ms))
for r, e in zip(tb.out_ms, expected_ms):
self.assertEqual(e, r)
def test_one(self):
"""
Tests split module and message stream combiner together.
"""
width = 32
sendnth = 2
max_packet_length = 10
n_packets = 20
data1 = []
for i in range(n_packets):
length = random.randint(0, max_packet_length)
packet = msg_utils.generate_random_packet(length,
config.msg_length_width,
width)
data1.extend(packet)
max_val = pow(2, width - 1) - 1
data2 = [random.randint(1, max_val) for i in range(len(data1))]
i_data = []
for d1, d2 in zip(data1, data2):
i_data.append(d1)
i_data.append(d2)
a_data = data1 + data2
padded_data = i_data + [0] * 1000
buffer_length = 128
defines = config.updated_defines({
'COMBINER_BUFFER_LENGTH':
buffer_length,
'LOG_COMBINER_BUFFER_LENGTH':
logceil(buffer_length),
'MAX_PACKET_LENGTH':
pow(2, config.msg_length_width),
'ERRORCODE':
666,
'WIDTH':
width,
})
executable = buildutils.generate_icarus_executable('message',
'splitcombiner',
'-test',
defines=defines)
fpgaimage = buildutils.generate_B100_image('message',
'splitcombiner',
'-test',
defines=defines)
tb_icarus = TestBenchIcarusOuter(executable,
in_raw=i_data,
sendnth=sendnth)
tb_b100 = TestBenchB100(fpgaimage, in_raw=padded_data)
for tb, steps in (
(tb_icarus, len(i_data) * sendnth * 2 + 1000),
(tb_b100, 100000),
):
tb.run(steps)
e_samples, e_packets = msg_utils.stream_to_samples_and_packets(
a_data, config.msg_length_width, width)
r_samples, r_packets = msg_utils.stream_to_samples_and_packets(
tb.out_raw, config.msg_length_width, width)
# Remove 0's from samples.
# The splitter can introduce 0's at beginning and end.
r_samples = [r for r in r_samples if r != 0]
self.assertEqual(len(e_samples), len(r_samples))
for e, r in zip(e_samples, r_samples):
self.assertEqual(e, r)
# Confirm all the packets are equal.
self.assertEqual(len(e_packets), len(r_packets))
for ep, rp in zip(e_packets, r_packets):
self.assertEqual(len(ep), len(rp))
for e, r in zip(ep, rp):
self.assertEqual(e, r)
def test_streams(self):
"""
Test the stream combiner a number of streams.
"""
width = 32
sendnth = 8
n_streams = 3
buffer_length = 128
max_packet_length = pow(2, config.msg_length_width)
defines = config.updated_defines(
{'N_STREAMS': n_streams,
'LOG_N_STREAMS': logceil(n_streams),
'WIDTH': width,
'INPUT_BUFFER_LENGTH': buffer_length,
'LOG_INPUT_BUFFER_LENGTH': logceil(buffer_length),
'MAX_PACKET_LENGTH': max_packet_length,
'LOG_MAX_PACKET_LENGTH': config.msg_length_width,
})
top_packet_length = 16
n_packets = 10
data_streams = []
packet_streams = []
data_stream = []
packet_stream = []
max_stream_length = 0
# Prob to start new packet.
prob_start = 0.1
for i in range(n_streams):
# data and packets have same content but packets is just
# broken into the packets
data, packets = msg_utils.generate_random_packets(
top_packet_length, n_packets, config.msg_length_width,
width, prob_start, self.rg)
max_stream_length = max(max_stream_length, len(data))
data_streams.append(data)
data_stream += data
packet_streams.append(packets)
packet_stream += packets
for ds in data_streams:
for i in range(max_stream_length - len(ds)):
ds.append(None)
expected_packet_dict = msg_utils.make_packet_dict(packet_stream)
combined_data = zip(*data_streams)
# How many steps are required to simulate the data.
steps_rqd = len(combined_data) * sendnth * 2 - 1000 # + 1000
# Create, setup and simulate the test bench.
executable = buildutils.generate_icarus_executable(
'message', 'message_stream_combiner', '-streams', defines)
tb = TestBenchMessageStreamCombiner(
executable, in_raw=combined_data, width=width)
tb.run(steps_rqd)
# Confirm that our method of converting a stream to packets is correct
packets_again = msg_utils.stream_to_packets(
data_stream, config.msg_length_width, width, allow_samples=False)
packet_dict_again = msg_utils.make_packet_dict(packets_again)
self.assertEqual(expected_packet_dict, packet_dict_again)
# Now use it on the ouput rather than the input.
received_packets = msg_utils.stream_to_packets(
tb.out_raw, config.msg_length_width, width, allow_samples=False)
received_packet_dict = msg_utils.make_packet_dict(received_packets)
self.assertEqual(expected_packet_dict, received_packet_dict)
def test_streams(self):
"""
Test the stream combiner a number of streams.
"""
width = 32
sendnth = 8
n_streams = 3
buffer_length = 128
max_packet_length = pow(2, config.msg_length_width)
defines = config.updated_defines({
'N_STREAMS':
n_streams,
'LOG_N_STREAMS':
logceil(n_streams),
'WIDTH':
width,
'INPUT_BUFFER_LENGTH':
buffer_length,
'LOG_INPUT_BUFFER_LENGTH':
logceil(buffer_length),
'MAX_PACKET_LENGTH':
max_packet_length,
'LOG_MAX_PACKET_LENGTH':
config.msg_length_width,
})
top_packet_length = 16
n_packets = 10
data_streams = []
packet_streams = []
data_stream = []
packet_stream = []
max_stream_length = 0
# Prob to start new packet.
prob_start = 0.1
for i in range(n_streams):
# data and packets have same content but packets is just
# broken into the packets
data, packets = msg_utils.generate_random_packets(
top_packet_length, n_packets, config.msg_length_width, width,
prob_start, self.rg)
max_stream_length = max(max_stream_length, len(data))
data_streams.append(data)
data_stream += data
packet_streams.append(packets)
packet_stream += packets
for ds in data_streams:
for i in range(max_stream_length - len(ds)):
ds.append(None)
expected_packet_dict = msg_utils.make_packet_dict(packet_stream)
combined_data = zip(*data_streams)
# How many steps are required to simulate the data.
steps_rqd = len(combined_data) * sendnth * 2 - 1000 # + 1000
# Create, setup and simulate the test bench.
executable = buildutils.generate_icarus_executable(
'message', 'message_stream_combiner', '-streams', defines)
tb = TestBenchMessageStreamCombiner(executable,
in_raw=combined_data,
width=width)
tb.run(steps_rqd)
# Confirm that our method of converting a stream to packets is correct
packets_again = msg_utils.stream_to_packets(data_stream,
config.msg_length_width,
width,
allow_samples=False)
packet_dict_again = msg_utils.make_packet_dict(packets_again)
self.assertEqual(expected_packet_dict, packet_dict_again)
# Now use it on the ouput rather than the input.
received_packets = msg_utils.stream_to_packets(tb.out_raw,
config.msg_length_width,
width,
allow_samples=False)
received_packet_dict = msg_utils.make_packet_dict(received_packets)
self.assertEqual(expected_packet_dict, received_packet_dict)
def test_bits(self):
"""
Tests the bits qa_wrapper.
"""
width = 32
sendnth = 70
max_sample = pow(2, width) - 1
n_samples = 2
data = [self.rg.randint(1, max_sample) for i in range(n_samples)]
defines = config.updated_defines({
'LOG_WIDTH': logceil(width),
'ERRORCODE': 666,
'WIDTH': width,
'LOG_SENDNTH': 12,
})
executable = buildutils.generate_icarus_executable('uhd',
'bits',
'-test',
defines=defines)
fpgaimage = buildutils.generate_B100_image('uhd',
'bits',
'-test',
defines=defines)
tb_icarus = TestBenchIcarusOuter(executable,
in_raw=data,
sendnth=sendnth)
tb_b100 = TestBenchB100(fpgaimage, in_raw=data)
for tb, steps in (
(tb_icarus, 5000),
(tb_b100, 100000),
):
tb.run(steps)
start_pos = None
for i, x in enumerate(tb.out_raw):
if (x == width - 1):
start_pos = i
break
for i, x in reversed(zip(range(0, len(tb.out_raw)), tb.out_raw)):
if (x == width - 1):
stop_pos = i
break
if start_pos is None:
raise ValueError("{0} not found in output".format(width - 1))
out = tb.out_raw[start_pos:stop_pos + 2 * width]
bitted = [
out[i * 2 * width + 1:(i + 1) * 2 * width + 1:2]
for i in range(len(out) / width / 2)
]
poses = [
out[i * 2 * width:(i + 1) * 2 * width:2]
for i in range(len(out) / width / 2)
]
expected = [31 - x for x in range(32)]
for i, p in enumerate(poses):
if (p != expected):
print(i)
print(p)
self.assertEqual(p, expected)
r_ints = [bits_to_int(bits) for bits in bitted]
r_ints = [x for x in r_ints if x != 0]
self.assertEqual(len(data), len(r_ints))
for e, r in zip(data, r_ints):
self.assertEqual(e, r)
def test_one(self):
"""
Test the stage module.
"""
width = config.default_width
sendnth = config.default_sendnth
# Changing N will require resynthesis.
N = 8
# Arguments used for producing verilog from templates.
extraargs = {}
# Amount of data to send.
n_data = 2 * N
# Define the input
in_samples = [
random.random() * 2 - 1 + random.random() * 2j - 1j
for i in range(n_data)
]
steps_rqd = len(in_samples) * sendnth + 100
# Define meta data
mwidth = 3
in_ms = [random.randint(0, pow(2, mwidth) - 1) for d in in_samples]
expected = in_samples
steps_rqd = n_data * sendnth * 2 + 1000
# Create, setup and simulate the test bench.
defines = config.updated_defines({
'WIDTH': width,
'MWIDTH': mwidth,
'N': N
})
executable_inner = buildutils.generate_icarus_executable(
'fft',
'stage_inner',
'-{0}'.format(N),
defines=defines,
extraargs=extraargs)
executable_outer = buildutils.generate_icarus_executable(
'fft',
'stage',
'-{0}'.format(N),
defines=defines,
extraargs=extraargs)
#fpgaimage = buildutils.generate_B100_image(
# 'fft', 'stage', '-{0}'.format(N), defines=defines,
# extraargs=extraargs)
tb_icarus_inner = TestBenchIcarusInner(executable_inner, in_samples,
in_ms)
tb_icarus_outer = TestBenchIcarusOuter(executable_outer, in_samples)
#tb_b100 = TestBenchB100(fpgaimage, in_samples)
for tb, steps, check_ms in (
(tb_icarus_inner, steps_rqd, True),
(tb_icarus_outer, steps_rqd, False),
#(tb_b100, 100000, False),
):
tb.run(steps)
# Confirm that our data is correct.
self.assertEqual(len(tb.out_samples), len(expected))
for r, e in zip(tb.out_samples, expected):
self.assertAlmostEqual(e, r, 3)
if check_ms:
self.assertEqual(len(tb.out_ms), len(in_ms))
for r, e in zip(tb.out_ms, in_ms):
self.assertEqual(e, r)
def test_one(self):
"""
Test the butterfly module.
"""
sendnth = 5
n_data = 1
width = 32
in_samples = []
expected = []
xas = [
random.random() * 2 - 1 + random.random() * 2j - 1j
for i in range(n_data)
]
xbs = [
random.random() * 2 - 1 + random.random() * 2j - 1j
for i in range(n_data)
]
# Max val of w is 10000 (roughly 0.5)
ws = [
0.5 * (random.random() * 2 - 1) + 0.5 * (random.random() * 2j - 1j)
for i in range(n_data)
]
for xa, xb, w in zip(xas, xbs, ws):
in_samples.append(xa)
in_samples.append(xb)
in_samples.append(w)
ya = xa + xb * w
yb = xa - xb * w
expected.append(ya / 2)
expected.append(yb / 2)
steps_rqd = len(in_samples) * sendnth * 2 + 100
# Define meta data
mwidth = 1
raw_ms = [random.randint(0, pow(2, mwidth) - 1) for i in range(n_data)]
in_ms = []
expected_ms = []
for m in raw_ms:
in_ms.extend((m, 0, 0))
expected_ms.extend((m, 0))
defines = config.updated_defines({
'DEBUG': True,
})
executable_inner = buildutils.generate_icarus_executable(
'fft', 'butterfly_inner', '-test', defines=defines)
executable_outer = buildutils.generate_icarus_executable(
'fft', 'butterfly', '-test', defines=defines)
#fpgaimage = buildutils.generate_B100_image(
# 'fft', 'butterfly', '-test', defines=defines)
tb_icarus_inner = TestBenchIcarusInner(executable_inner,
in_samples,
in_ms,
sendnth=sendnth)
tb_icarus_outer = TestBenchIcarusOuter(executable_outer,
in_samples,
sendnth=sendnth)
#tb_b100 = TestBenchB100(fpgaimage, in_samples)
for tb, steps, check_ms in (
(tb_icarus_inner, steps_rqd, True),
(tb_icarus_outer, steps_rqd, False),
#(tb_b100, 100000, False),
):
tb.run(steps)
# Confirm that our data is correct.
print(tb.out_raw)
print(tb.out_samples)
print(expected)
self.assertEqual(len(tb.out_samples), len(expected))
for msg in tb.out_messages:
print("message is")
print(msg)
xa = int_to_c(msg[1], width / 2 - 1)
xbw = int_to_c(msg[2], width / 2 - 1)
ya = int_to_c(msg[3], width / 2 - 1)
yb = int_to_c(msg[4], width / 2 - 1)
print("e xa is {0} xbw is {1}".format(xas[0] / 2,
xbs[0] * ws[0] / 2))
print("r xa is {0} xbw is {1}".format(xa, xbw))
for r, e in zip(tb.out_samples, expected):
print(e, r)
self.assertAlmostEqual(e, r, 3)
if check_ms:
self.assertEqual(len(tb.out_ms), len(expected_ms))
for r, e in zip(tb.out_ms, expected_ms):
self.assertEqual(e, r)
def test_one(self):
"""
Test the filterbank module.
"""
width = config.default_width
sendnth = config.default_sendnth
# Changing filter_length will require resynthesis.
n_filters = 3
filter_length = 3
all_taps = []
combined_taps = []
for n in range(n_filters):
taps = [random.random()*2-1 for i in range(filter_length)]
total = sum([abs(t) for t in taps])
taps = [t/total for t in taps]
all_taps.append(taps)
combined_taps.extend(taps)
# Arguments used for producing verilog from templates.
extraargs = {'summult_length': filter_length,}
# Amount of data to send.
n_data = 30
# Define the input
in_samples = [0]*filter_length*n_filters*2
in_samples += [random.random()*2-1 + random.random()*2j-1j for i in range(n_data)]
in_samples += [0]*(filter_length-1)*n_filters
steps_rqd = len(in_samples)*sendnth + 100
# Define meta data
mwidth = 1
in_ms = [random.randint(0, pow(2,mwidth)-1) for d in in_samples]
possible_expected = []
for m in range(n_filters):
shifted_taps = all_taps[m:] + all_taps[:m]
expected_outputs = []
for n in range(n_filters):
filter_inputs = in_samples[n::n_filters]
convolved = convolve(filter_inputs, shifted_taps[n])
expected_outputs.append(convolved)
expected = []
for eo in zip(*expected_outputs):
expected.extend(eo)
possible_expected.append(expected)
steps_rqd = n_data * sendnth * 2 + 1000
# Create, setup and simulate the test bench.
filter_id = 123
defines = config.updated_defines(
{'WIDTH': width,
'FILTER_LENGTH': filter_length,
'FILTERBANK_ID': filter_id,
'N_FILTERS': n_filters,
'FILTERBANK_MSG_BUFFER_LENGTH': 128,
})
executable_inner = buildutils.generate_icarus_executable(
'flter', 'filterbank_inner', '-test', defines=defines, extraargs=extraargs)
executable_outer = buildutils.generate_icarus_executable(
'flter', 'filterbank', '-test', defines=defines, extraargs=extraargs)
fpgaimage = buildutils.generate_B100_image(
'flter', 'filterbank', '-test', defines=defines,
extraargs=extraargs)
start_msgs = taps_to_start_msgs(combined_taps, defines['WIDTH']/2, filter_id)
tb_icarus_inner = TestBenchIcarusInner(executable_inner, in_samples, in_ms, start_msgs)
tb_icarus_outer = TestBenchIcarusOuter(executable_outer, in_samples, start_msgs)
tb_b100 = TestBenchB100(fpgaimage, in_samples, start_msgs)
for tb, steps in (
(tb_icarus_inner, steps_rqd),
(tb_icarus_outer, steps_rqd),
(tb_b100, 100000),
):
tb.run(steps)
# Confirm that our data is correct.
received = prune_zeros(tb.out_samples)
tol = 0.001
matched_once = False
for expected in possible_expected:
expected = prune_zeros(expected)
matches = True
if (len(received) != len(expected)):
matches = False
else:
for r, e in zip(received, expected):
if (abs(r-e) > tol):
matches = False
break
if matches:
matched_once = True
self.assertTrue(matched_once)
def test_one(self):
"""
Test the filter module.
"""
width = config.default_width
sendnth = config.default_sendnth
# Changing filter_length will require resynthesis.
filter_length = 4
taps = [random.random() * 2 - 1 for i in range(filter_length)]
total = sum([abs(t) for t in taps])
taps = [t / total for t in taps]
# Arguments used for producing verilog from templates.
extraargs = {
'summult_length': filter_length,
}
# Amount of data to send.
n_data = 10
# Define the input
in_samples = [
random.random() * 2 - 1 + random.random() * 2j - 1j
for i in range(n_data)
]
in_samples += [0] * (filter_length - 1)
steps_rqd = len(in_samples) * sendnth + 100
# Define meta data
mwidth = 1
in_ms = [random.randint(0, pow(2, mwidth) - 1) for d in in_samples]
expected = convolve(in_samples, taps)
steps_rqd = n_data * sendnth * 2 + 1000
filter_id = 123
# Create, setup and simulate the test bench.
defines = config.updated_defines({
'WIDTH': width,
'FILTER_LENGTH': filter_length,
'FILTER_ID': filter_id,
})
executable_inner = buildutils.generate_icarus_executable(
'flter',
'filter_inner',
'-test',
defines=defines,
extraargs=extraargs)
executable_outer = buildutils.generate_icarus_executable(
'flter', 'filter', '-test', defines=defines, extraargs=extraargs)
fpgaimage = buildutils.generate_B100_image('flter',
'filter',
'-test',
defines=defines,
extraargs=extraargs)
start_msgs = taps_to_start_msgs(taps, defines['WIDTH'] / 2, filter_id)
tb_icarus_inner = TestBenchIcarusInner(executable_inner, in_samples,
in_ms, start_msgs)
tb_icarus_outer = TestBenchIcarusOuter(executable_outer, in_samples,
start_msgs)
tb_b100 = TestBenchB100(fpgaimage, in_samples, start_msgs)
for tb, steps in (
(tb_icarus_inner, steps_rqd),
(tb_icarus_outer, steps_rqd),
(tb_b100, 100000),
):
tb.run(steps)
# Confirm that our data is correct.
self.assertEqual(len(tb.out_samples), len(expected))
for r, e in zip(tb.out_samples, expected):
self.assertAlmostEqual(e, r, 3)
def test_one(self):
"""
Test the filterbank module.
"""
width = config.default_width
sendnth = config.default_sendnth
# Changing filter_length will require resynthesis.
n_filters = 3
filter_length = 3
all_taps = []
combined_taps = []
for n in range(n_filters):
taps = [random.random() * 2 - 1 for i in range(filter_length)]
total = sum([abs(t) for t in taps])
taps = [t / total for t in taps]
all_taps.append(taps)
combined_taps.extend(taps)
# Arguments used for producing verilog from templates.
extraargs = {
'summult_length': filter_length,
}
# Amount of data to send.
n_data = 30
# Define the input
in_samples = [0] * filter_length * n_filters * 2
in_samples += [
random.random() * 2 - 1 + random.random() * 2j - 1j
for i in range(n_data)
]
in_samples += [0] * (filter_length - 1) * n_filters
steps_rqd = len(in_samples) * sendnth + 100
# Define meta data
mwidth = 1
in_ms = [random.randint(0, pow(2, mwidth) - 1) for d in in_samples]
possible_expected = []
for m in range(n_filters):
shifted_taps = all_taps[m:] + all_taps[:m]
expected_outputs = []
for n in range(n_filters):
filter_inputs = in_samples[n::n_filters]
convolved = convolve(filter_inputs, shifted_taps[n])
expected_outputs.append(convolved)
expected = []
for eo in zip(*expected_outputs):
expected.extend(eo)
possible_expected.append(expected)
steps_rqd = n_data * sendnth * 2 + 1000
# Create, setup and simulate the test bench.
filter_id = 123
defines = config.updated_defines({
'WIDTH': width,
'FILTER_LENGTH': filter_length,
'FILTERBANK_ID': filter_id,
'N_FILTERS': n_filters,
'FILTERBANK_MSG_BUFFER_LENGTH': 128,
})
executable_inner = buildutils.generate_icarus_executable(
'flter',
'filterbank_inner',
'-test',
defines=defines,
extraargs=extraargs)
executable_outer = buildutils.generate_icarus_executable(
'flter',
'filterbank',
'-test',
defines=defines,
extraargs=extraargs)
fpgaimage = buildutils.generate_B100_image('flter',
'filterbank',
'-test',
defines=defines,
extraargs=extraargs)
start_msgs = taps_to_start_msgs(combined_taps, defines['WIDTH'] / 2,
filter_id)
tb_icarus_inner = TestBenchIcarusInner(executable_inner, in_samples,
in_ms, start_msgs)
tb_icarus_outer = TestBenchIcarusOuter(executable_outer, in_samples,
start_msgs)
tb_b100 = TestBenchB100(fpgaimage, in_samples, start_msgs)
for tb, steps in (
(tb_icarus_inner, steps_rqd),
(tb_icarus_outer, steps_rqd),
(tb_b100, 100000),
):
tb.run(steps)
# Confirm that our data is correct.
received = prune_zeros(tb.out_samples)
tol = 0.001
matched_once = False
for expected in possible_expected:
expected = prune_zeros(expected)
matches = True
if (len(received) != len(expected)):
matches = False
else:
for r, e in zip(received, expected):
if (abs(r - e) > tol):
matches = False
break
if matches:
matched_once = True
self.assertTrue(matched_once)
