def add_module_owire_port(self, name, eqd):
""" Add the specified eqd as an output wire port of the module. """
a = Attrib(names.give('ow_{0}'.format(name)), None)
a.set_eqdef(eqd)
self.add_eqs([a])
wp = ModWirePort(ModWirePort.OUT, name, NId(a.get_core()))
self.all_modwireports.append(wp)
def add_port_from(self, pname, dtype):
at = Attrib(names.give('iw_{0}_{1}'.format(self.iname, pname)), dtype)
# self.mod.add_eqs([at])
at.get_core().mark_as_necessary()
at.get_core().set_allow_subst(False)
# create the wire port of the instance
wp = ModWirePort(ModWirePort.OUT, pname, NId(at.get_core()))
self.wireports.append(wp)
return at.get_core()
def add_port_to(self, pname, eqval):
""" Add new port named 'pname', input to the instance, driven by eqval. """
# an attribute through which the output signal is routed
at = Attrib(names.give('ow_{0}_{1}'.format(self.iname, pname)), None)
if eqval:
at.set_eqdef(eqval)
self.mod.add_eqs([at])
at.get_core().mark_as_necessary()
# create the wire port of the instance
wp = ModWirePort(ModWirePort.IN, pname, NId(at.get_core()))
self.wireports.append(wp)
return at.get_core()
def explicit_port_drivers(self):
""" Drivers for the module ports:
At the beginning each port's WAND serves as both an input and output
for external logic. During cycle elimination however the edges may be
moved around. Thus at the end the input edge (external driver)
will be disambiguated in mp.attr_FI
"""
for mp in self.all_modports:
a = mp.get_F_core()
dr_attr = Attrib(names.give(a.get_name()), a.get_actype(), a.get_ackind())
dr = dr_attr.get_core()
# self.all_undefs.add(dr) overwriten in extract_undefs()
dr.mark_as_necessary()
mp.attr_FI = dr_attr
mp.get_F_core().wand_add(NId(dr))