def test_resources_b(self):
u = ListOfInterfacesSample3b()
expected = {}
s = ResourceAnalyzer()
toRtl(u, serializer=s)
self.assertDictEqual(s.report(), expected)
def test_resources_b(self):
u = ListOfInterfacesSample3b()
expected = {}
s = ResourceAnalyzer()
toRtl(u, serializer=s)
self.assertDictEqual(s.report(), expected)
def test_latch_in_switch(self):
u = LatchInSwitchTest()
ra = ResourceAnalyzer()
synthesised(u)
ra.visit_Unit(u)
res = ra.report()
expected = {(ResourceMUX, 4, 6): 1, ResourceLatch: 4}
self.assertDictEqual(res, expected)
def test_resources_b(self):
u = ListOfInterfacesSample3b()
expected = {}
s = ResourceAnalyzer()
synthesised(u)
s.visit_Unit(u)
self.assertDictEqual(s.report(), expected)
def test_BoolToBits(self):
u = BoolToBitTest()
ra = ResourceAnalyzer()
toRtl(u, serializer=ra)
res = ra.report()
expected = {
(AllOps.EQ, 4): 1,
}
self.assertDictEqual(res, expected)
def test_resources(self):
u = SwitchStmUnit()
expected = {(ResourceMUX, 1, 4): 1}
s = ResourceAnalyzer()
toRtl(u, serializer=s)
r = s.report()
self.assertDictEqual(r, expected)
def test_resources_SimpleIfStatement3(self):
u = SimpleIfStatement3()
expected = {}
s = ResourceAnalyzer()
toRtl(u, serializer=s)
r = s.report()
self.assertDictEqual(r, expected)
def test_latch_resources(self):
u = Latch()
expected = {
ResourceLatch: 1,
}
s = ResourceAnalyzer()
toRtl(u, serializer=s)
self.assertDictEqual(s.report(), expected)
def test_sync_resources(self):
u = SimpleSyncRom()
expected = {
ResourceRAM(8, 4, 0, 1, 0, 0, 0, 0, 0, 0): 1,
}
s = ResourceAnalyzer()
toRtl(u, serializer=s)
self.assertDictEqual(s.report(), expected)
def test_resources(self):
u = SwitchStmUnit()
expected = {(ResourceMUX, 1, 4): 1}
s = ResourceAnalyzer()
toRtl(u, serializer=s)
r = s.report()
self.assertDictEqual(r, expected)
def test_resources(self):
u = SwitchStmUnit()
expected = {(ResourceMUX, 1, 4): 1}
s = ResourceAnalyzer()
synthesised(u)
s.visit_Unit(u)
r = s.report()
self.assertDictEqual(r, expected)
def test_resources_SimpleIfStatement3(self):
u = SimpleIfStatement3()
expected = {}
s = ResourceAnalyzer()
synthesised(u)
s.visit_Unit(u)
r = s.report()
self.assertDictEqual(r, expected)
def test_resources_SimpleIfStatement3(self):
u = SimpleIfStatement3()
expected = {
}
s = ResourceAnalyzer()
toRtl(u, serializer=s)
r = s.report()
self.assertDictEqual(r, expected)
def test_BoolToBits(self):
u = BoolToBitTest()
ra = ResourceAnalyzer()
synthesised(u)
ra.visit_Unit(u)
res = ra.report()
expected = {
(AllOps.EQ, 4): 1,
}
self.assertDictEqual(res, expected)
def test_sync_resources(self):
u = SimpleSyncRam()
expected = {
ResourceRAM(8, 4, 0, 1, 1, 0, 0, 0, 0, 0): 1,
}
s = ResourceAnalyzer()
synthesised(u)
s.visit_Unit(u)
self.assertDictEqual(s.report(), expected)
def test_latch_in_switch(self):
u = LatchInSwitchTest()
ra = ResourceAnalyzer()
toRtl(u, serializer=ra)
res = ra.report()
expected = {
(ResourceMUX, 4, 6): 1,
ResourceLatch: 4
}
self.assertDictEqual(res, expected)
def test_latch_resources(self):
u = Latch()
expected = {
ResourceLatch: 1,
}
s = ResourceAnalyzer()
synthesised(u)
s.visit_Unit(u)
self.assertDictEqual(s.report(), expected)
def test_sync_resources(self):
u = SimpleSyncRom()
expected = {
ResourceRAM(8, 4,
0, 1, 0, 0,
0, 0, 0, 0): 1,
}
s = ResourceAnalyzer()
toRtl(u, serializer=s)
self.assertDictEqual(s.report(), expected)
def test_resources_2b(self):
u = Cntr()
expected = {(AllOps.ADD, 2): 1,
# 1 for reset, one for en
(ResourceMUX, 2, 2): 2,
ResourceFF: 2}
s = ResourceAnalyzer()
toRtl(u, serializer=s)
r = s.report()
self.assertDictEqual(r, expected)
def test_resources_150b(self):
u = Cntr()
u.DATA_WIDTH.set(150)
expected = {(AllOps.ADD, 150): 1,
# 1 for reset, one for en
(ResourceMUX, 150, 2): 2,
ResourceFF: 150}
s = ResourceAnalyzer()
toRtl(u, serializer=s)
r = s.report()
self.assertDictEqual(r, expected)
def test_resources_2b(self):
u = Cntr()
expected = {
(AllOps.ADD, 2): 1,
# 1 for reset, one for en
(ResourceMUX, 2, 2): 2,
ResourceFF: 2
}
s = ResourceAnalyzer()
toRtl(u, serializer=s)
r = s.report()
self.assertDictEqual(r, expected)
def test_resources_150b(self):
u = Cntr()
u.DATA_WIDTH.set(150)
expected = {
(AllOps.ADD, 150): 1,
# 1 for reset, one for en
(ResourceMUX, 150, 2): 2,
ResourceFF: 150
}
s = ResourceAnalyzer()
toRtl(u, serializer=s)
r = s.report()
self.assertDictEqual(r, expected)
def test_resources_SimpleIfStatement2c(self):
u = SimpleIfStatement2c()
expected = {
(AllOps.AND, 1): 1,
(AllOps.EQ, 1): 1,
(ResourceMUX, 2, 2): 1,
(ResourceMUX, 2, 4): 1,
ResourceFF: 2,
}
s = ResourceAnalyzer()
toRtl(u, serializer=s)
r = s.report()
self.assertDictEqual(r, expected)
def test_resources_SimpleIfStatement2c(self):
u = SimpleIfStatement2c()
expected = {
(AllOps.AND, 1): 1,
(AllOps.EQ, 1): 1,
(ResourceMUX, 2, 2): 1,
(ResourceMUX, 2, 4): 1,
ResourceFF: 2,
}
s = ResourceAnalyzer()
toRtl(u, serializer=s)
r = s.report()
self.assertDictEqual(r, expected)
def test_resources_SimpleIfStatement2c(self):
u = SimpleIfStatement2c()
expected = {
(AllOps.AND, 1): 1,
(AllOps.EQ, 1): 1,
(ResourceMUX, 2, 2): 1,
(ResourceMUX, 2, 4): 1,
ResourceFF: 2,
}
s = ResourceAnalyzer()
synthesised(u)
s.visit_Unit(u)
r = s.report()
self.assertDictEqual(r, expected)
fRam[r1](a, fit=True),
self.k(fRam[r1]._unsigned(), fit=True)
)
if __name__ == "__main__": # alias python main function
from pprint import pprint
from hwt.synthesizer.utils import to_rtl_str
from hwt.serializer.hwt import HwtSerializer
from hwt.serializer.vhdl import Vhdl2008Serializer
from hwt.serializer.verilog import VerilogSerializer
from hwt.serializer.systemC import SystemCSerializer
from hwt.serializer.resourceAnalyzer.analyzer import ResourceAnalyzer
from hwt.synthesizer.utils import synthesised
# * new instance has to be created every time because to_rtl_str modifies the unit
# * serializers are using templates which can be customized
# serialized code is trying to be human and git friendly
print(to_rtl_str(Showcase0(), serializer_cls=HwtSerializer))
print(to_rtl_str(Showcase0(), serializer_cls=Vhdl2008Serializer))
print(to_rtl_str(Showcase0(), serializer_cls=VerilogSerializer))
print(to_rtl_str(Showcase0(), serializer_cls=SystemCSerializer))
u = Showcase0()
ra = ResourceAnalyzer()
synthesised(u)
ra.visit_Unit(u)
pprint(ra.report())
def visit_HdlModuleDef(self, m: HdlModuleDef) -> None:
ResourceAnalyzer.visit_HdlModuleDef(self, m)
# note that rams are usually working on rising edge
fRam = self._sig("fallingEdgeRam", int8_t[4])
If(self.clk._onFallingEdge(),
# fit can extend signal and also shrink it
connect(a, fRam[r1], fit=True),
connect(fRam[r1]._unsigned(), self.k, fit=True)
)
if __name__ == "__main__": # alias python main function
from pprint import pprint
from hwt.synthesizer.utils import toRtl
from hwt.serializer.hwt.serializer import HwtSerializer
from hwt.serializer.vhdl.serializer import VhdlSerializer
from hwt.serializer.verilog.serializer import VerilogSerializer
from hwt.serializer.systemC.serializer import SystemCSerializer
from hwt.serializer.resourceAnalyzer.analyzer import ResourceAnalyzer
# * new instance has to be created every time because toRtl is modifies the unit
# * serializers are using templates which can be customized
# serialized code is trying to be human and git friednly
print(toRtl(Showcase0(), serializer=HwtSerializer))
print(toRtl(Showcase0(), serializer=VhdlSerializer))
print(toRtl(Showcase0(), serializer=VerilogSerializer))
print(toRtl(Showcase0(), serializer=SystemCSerializer))
r = ResourceAnalyzer()
print(toRtl(Showcase0(), serializer=r))
pprint(r.report())