def test_latch_in_switch(self):
u = LatchInSwitchTest()
ra = ResourceAnalyzer()
synthesised(u)
ra.visit_Unit(u)
res = ra.report()
expected = {(ResourceMUX, 4, 6): 1, ResourceLatch: 4}
self.assertDictEqual(res, expected)
def test_resources_b(self):
u = ListOfInterfacesSample3b()
expected = {}
s = ResourceAnalyzer()
synthesised(u)
s.visit_Unit(u)
self.assertDictEqual(s.report(), expected)
def test_latch_resources(self):
u = Latch()
expected = {
ResourceLatch: 1,
}
s = ResourceAnalyzer()
synthesised(u)
s.visit_Unit(u)
self.assertDictEqual(s.report(), expected)
def test_BoolToBits(self):
u = BoolToBitTest()
ra = ResourceAnalyzer()
synthesised(u)
ra.visit_Unit(u)
res = ra.report()
expected = {
(AllOps.EQ, 4): 1,
}
self.assertDictEqual(res, expected)
def test_resources(self):
u = SwitchStmUnit()
expected = {(ResourceMUX, 1, 4): 1}
s = ResourceAnalyzer()
synthesised(u)
s.visit_Unit(u)
r = s.report()
self.assertDictEqual(r, expected)
def test_resources_SimpleIfStatement3(self):
u = SimpleIfStatement3()
expected = {}
s = ResourceAnalyzer()
synthesised(u)
s.visit_Unit(u)
r = s.report()
self.assertDictEqual(r, expected)
def test_sync_resources(self):
u = SimpleSyncRam()
expected = {
ResourceRAM(8, 4, 0, 1, 1, 0, 0, 0, 0, 0): 1,
}
s = ResourceAnalyzer()
synthesised(u)
s.visit_Unit(u)
self.assertDictEqual(s.report(), expected)
def test_resources_SimpleIfStatement2c(self):
u = SimpleIfStatement2c()
expected = {
(AllOps.AND, 1): 1,
(AllOps.EQ, 1): 1,
(ResourceMUX, 2, 2): 1,
(ResourceMUX, 2, 4): 1,
ResourceFF: 2,
}
s = ResourceAnalyzer()
synthesised(u)
s.visit_Unit(u)
r = s.report()
self.assertDictEqual(r, expected)
fRam[r1](a, fit=True),
self.k(fRam[r1]._unsigned(), fit=True)
)
if __name__ == "__main__": # alias python main function
from pprint import pprint
from hwt.synthesizer.utils import to_rtl_str
from hwt.serializer.hwt import HwtSerializer
from hwt.serializer.vhdl import Vhdl2008Serializer
from hwt.serializer.verilog import VerilogSerializer
from hwt.serializer.systemC import SystemCSerializer
from hwt.serializer.resourceAnalyzer.analyzer import ResourceAnalyzer
from hwt.synthesizer.utils import synthesised
# * new instance has to be created every time because to_rtl_str modifies the unit
# * serializers are using templates which can be customized
# serialized code is trying to be human and git friendly
print(to_rtl_str(Showcase0(), serializer_cls=HwtSerializer))
print(to_rtl_str(Showcase0(), serializer_cls=Vhdl2008Serializer))
print(to_rtl_str(Showcase0(), serializer_cls=VerilogSerializer))
print(to_rtl_str(Showcase0(), serializer_cls=SystemCSerializer))
u = Showcase0()
ra = ResourceAnalyzer()
synthesised(u)
ra.visit_Unit(u)
pprint(ra.report())