def __init__(self, input_data: Signal, sync_pattern=(-1, 0, 0)):
"""
Aligns the word boundries of one Hispi lane and detects control codes.
Compatible only with Packetized-SP mode because it needs end markers.
:param sync_pattern: the preamble of a control word (default is correct for most cases)
:param timeout: Issue a bit slip after a control word wasnt found for n cycles
"""
self.sync_pattern = sync_pattern
self.input_data = input_data
self.is_aligned = StatusSignal()
self.timeout = ControlSignal(32, reset=10000)
self.timeouts_to_resync = ControlSignal(32, reset=10000)
self.since_last_sync_pattern_or_bitslip = StatusSignal(32)
self.performed_bitslips = StatusSignal(32)
self.timeouts_since_alignment = StatusSignal(32)
self.last_word = StatusSignal(input_data.shape())
self.last_control_word = StatusSignal(
input_data.shape(),
decoder=lambda x: next(
("{}/{:012b}".format(control_word, x)
for control_word, ending in control_words.items() if "{:012b}"
.format(x).endswith(ending)), "UNKNOWN/{:012b}".format(x)))
self.do_bitslip = Signal()
self.output = ImageStream(self.input_data.shape())
def __init__(self, num_lanes, bits):
assert num_lanes <= 32 # the pulse registers cannot be made wider
assert bits == 12 # patterns, bitslip counts, and validation need adjusting
self.num_lanes = num_lanes
self.bits = bits
self.lane_pattern = ControlSignal(bits)
# registers accessed by host
self.data_lane_delay_reset = PulseReg(num_lanes)
self.data_lane_delay_inc = PulseReg(num_lanes)
self.data_lane_bitslip = PulseReg(num_lanes)
self.data_lane_match = StatusSignal(num_lanes)
self.data_lane_mismatch = StatusSignal(num_lanes)
self.ctrl_lane_delay_reset = PulseReg(2) # control and clock
self.ctrl_lane_delay_inc = PulseReg(2)
self.ctrl_lane_bitslip = PulseReg(2)
self.ctrl_lane_match = StatusSignal(1)
self.ctrl_lane_mismatch = StatusSignal(1)
self.trained = ControlSignal(1)
# signals to/from PHY
self.lane_delay_reset = Signal(num_lanes + 1)
self.lane_delay_inc = Signal(num_lanes + 1)
self.lane_bitslip = Signal(num_lanes + 1)
self.outclk_delay_reset = Signal()
self.outclk_delay_inc = Signal()
self.halfslip = Signal()
self.lane_match = Signal(num_lanes + 1)
self.lane_mismatch = Signal(num_lanes + 1)
def __init__(self, pin):
self.pin = pin
self.delay = ControlSignal(5)
self.load = ControlSignal()
self.output = Signal()
def __init__(self, i):
self.i = i
self.move = ControlSignal()
self.direction = ControlSignal()
self.at_limit = StatusSignal()
self.o = Signal()
def __init__(self, input: ImageStream, width=3000, height=3000):
self.input = input
self.output = ImageStream(24)
self.width = width
self.height = height
self.shift_x = ControlSignal()
self.shift_y = ControlSignal()
def __init__(self, input: ImageStream, desired_width, desired_height):
self.input = input
self.output = input.clone(name="resized")
self.output_width = ControlSignal(16, reset=desired_width)
self.output_height = ControlSignal(16, reset=desired_height)
self.shift_x = ControlSignal(signed(16))
self.shift_y = ControlSignal(signed(16))
self.input_width = StatusSignal(16)
self.input_height = StatusSignal(16)
def __init__(self, input: ImageStream, width=3000, height=3000):
self.input = input
self.output = ImageStream(24)
self.width = width
self.height = height
self.threshold = ControlSignal(16, reset=255)
self.highlight_r = ControlSignal(8, reset=255)
self.highlight_g = ControlSignal(8)
self.highlight_b = ControlSignal(8)
def __init__(self, input: ImageStream, hdmi):
self.hdmi = hdmi
self.input = input
self.allow_slip_h = ControlSignal(reset=1)
self.allow_slip_v = ControlSignal(reset=1)
self.slipped_v = StatusSignal(32)
self.slipped_h = StatusSignal(32)
self.line_cycles = StatusSignal(32)
self.frame_cycles = StatusSignal(32)
def __init__(self,
plugin_resource,
input: BasicStream,
bitclk_domain,
training_pattern=0b00010110):
self.bitclk_domain = bitclk_domain
self.plugin_resource = plugin_resource
self.input = input
self.training_pattern = ControlSignal(8, reset=training_pattern)
self.do_training = ControlSignal(reset=1)
def __init__(self, data_width=8, max_packet_size=1024):
self.max_packet_size = max_packet_size
self.reset = ControlSignal()
self.packet_length = ControlSignal(range(max_packet_size))
self.read_ptr = StatusSignal(range(max_packet_size))
self.done = StatusSignal(reset=1)
self.memory = SocMemory(
width=data_width, depth=self.max_packet_size,
soc_read=False, attrs=dict(syn_ramstyle="block_ram")
)
self.output = PacketizedStream(data_width)
def __init__(self, num_lanes=4, bits=12, hispi_domain="hispi"):
assert bits == 12
self.hispi_domain = hispi_domain
self.hispi_clk = Signal()
self.hispi_lanes = Signal(num_lanes)
self.bitslip = [Signal() for _ in range(num_lanes)]
self.out = [Signal(12) for _ in range(num_lanes)]
self.hispi_x6_in_domain_counter = StatusSignal(32)
self.enable_bitslip = ControlSignal(reset=1)
self.word_reverse = ControlSignal()
def __init__(self, resource, modeline, pix_domain="pix", generate_clocks=True):
self.resource = resource
self.pix_domain = pix_domain
self.generate_clocks = generate_clocks
self.initial_video_timing = parse_modeline(modeline)
self.pix_freq = Clock(self.initial_video_timing.pxclk * 1e6)
self.rgb = RGB24()
self.hsync_polarity = ControlSignal()
self.vsync_polarity = ControlSignal()
self.clock_pattern = ControlSignal(10, name="hdmi_clock_pattern", reset=0b1111100000)
self.timing_generator = HdmiTimingGenerator(self.initial_video_timing)
def __init__(self, pin, ddr_domain):
self.pin = pin
self.ddr_domain = ddr_domain
self.bitslip = ControlSignal()
self.output = Signal(8)
def __init__(self, ddr_domain, lane_output):
self.ddr_domain = ddr_domain
self.lane_output = lane_output
self.do_bitslip = ControlSignal()
self.bitslip = Signal()
def __init__(self, plugin, domain_name="sync"):
self.plugin = plugin
self.output = BasicStream(32)
self.domain_name = domain_name
self.trained = ControlSignal()
self.valid = StatusSignal()
def __init__(self, trace_length=2048, after_trigger=None):
self.trace_length = trace_length
self.after_trigger = ControlSignal(
range(trace_length),
reset=(trace_length //
2 if after_trigger is None else after_trigger))
self.reset = ControlSignal()
# Yosys cannot handle a signal named `initial` (bug #2914)
self.initial_ = StatusSignal(reset=1)
self.running = StatusSignal()
self.write_ptr = StatusSignal(range(trace_length))
self.trigger_since = StatusSignal(range(trace_length + 1))
self.probes = []
self.decoders = []
def __init__(self, input: BasicStream, output_width):
self.input = input
self.output_width = output_width
self.offset = ControlSignal(
range(len(self.input.payload) - self.output_width))
self.output = self.input.clone()
self.output.payload = Signal(self.output_width)
def __init__(self,
input: ImageStream,
num_lanes: int,
image_width=480,
debug=False):
assert len(input.payload) == 24
self.input = input
self.num_lanes = num_lanes
self.image_width = ControlSignal(16, reset=image_width * 3)
self.debug = debug
self.vbp = ControlSignal(16, reset=18)
self.vfp = ControlSignal(16, reset=4)
self.hbp = ControlSignal(16, reset=68 * 3)
self.hfp = ControlSignal(16, reset=20 * 3)
self.gearbox_not_ready = StatusSignal(32)
self.output = PacketizedStream(num_lanes * 8)
def __init__(self, resource, num_lanes, ddr_domain, ck_domain):
self.resource = resource
self.num_lanes = num_lanes
self.ddr_domain = ddr_domain
self.ck_domain = ck_domain
self.control_input = PacketizedStream(8)
self.control_output = PacketizedStream(8)
self.hs_input = PacketizedStream(8 * num_lanes)
self.request_hs = ControlSignal()
def test_simple_test_csr_bank(self):
platform = ZynqSocPlatform(SimPlatform())
csr_bank = CsrBank()
csr_bank.reg("csr", ControlSignal(32))
def testbench():
axi: AxiEndpoint = platform.axi_lite_master
yield axi.read_address.payload.eq(0x4000_0000)
yield axi.read_address.valid.eq(1)
yield from do_nothing()
platform.sim(csr_bank, (testbench, "axi_lite"))
def __init__(self, input: PacketizedStream, max_packet_size=1024):
self.max_packet_size = max_packet_size
self.reset = ControlSignal()
self.write_pointer = StatusSignal(range(self.max_packet_size))
self.packet_done = StatusSignal()
self.memory = SocMemory(
width=len(input.payload), depth=self.max_packet_size,
soc_write=False, attrs=dict(syn_ramstyle="block_ram")
)
self.input = input
def check_csr_bank(self, num_csr=10, testdata=0x12345678, use_axi_interconnect=False):
platform = ZynqSocPlatform(SimPlatform(), use_axi_interconnect)
csr_bank = CsrBank()
for i in range(num_csr):
csr_bank.reg("csr#{}".format(i), ControlSignal(32))
def testbench():
axi = platform.axi_lite_master
for addr in [0x4000_0000 + (i * 4) for i in range(num_csr)]:
yield from axil_read(axi, addr)
yield from axil_write(axi, addr, testdata)
self.assertEqual(testdata, (yield from axil_read(axi, addr)))
platform.sim(csr_bank, (testbench, "axi_lite"))
def __init__(self, input: PacketizedStream, packet_len):
self.input = input
self.output = BasicStream(input.payload.shape())
# we calculate everything in bytes to make it easier to reason about
buffer_size = 2048 * 4
blanking = buffer_size
aligned_len = ceil((packet_len + blanking) / buffer_size) * buffer_size
print("ft60x paddnig:", (aligned_len - packet_len),
(aligned_len - packet_len) // 4)
self.padding = ControlSignal(16, reset=(aligned_len - packet_len) // 4)
self.frame_len = StatusSignal(32)
self.frame_len_changed = StatusSignal(32)
def __init__(self, video_timing, vertical_signals_shape=range(8000), horizontal_signals_shape=range(4000)):
self.hscan = ControlSignal(horizontal_signals_shape, reset=video_timing.hscan)
self.vscan = ControlSignal(vertical_signals_shape, reset=video_timing.vscan)
self.width = ControlSignal(horizontal_signals_shape, reset=video_timing.hres)
self.height = ControlSignal(vertical_signals_shape, reset=video_timing.vres)
self.hsync_start = ControlSignal(horizontal_signals_shape, reset=video_timing.hsync_start)
self.hsync_end = ControlSignal(horizontal_signals_shape, reset=video_timing.hsync_end)
self.vsync_start = ControlSignal(vertical_signals_shape, reset=video_timing.vsync_start)
self.vsync_end = ControlSignal(vertical_signals_shape, reset=video_timing.vsync_end)
self.x = StatusSignal(horizontal_signals_shape,)
self.y = StatusSignal(vertical_signals_shape)
self.active = StatusSignal()
self.is_blanking_x = StatusSignal()
self.is_blanking_y = StatusSignal()
self.hsync = StatusSignal()
self.vsync = StatusSignal()
def __init__(self, input, in_testpattern_mode, ddr_domain, bitslip_signal, testpattern=0b00010110):
"""
Does bit alignment of one lane usig a given testpattern if in_testpattern_mode is high
"""
self.input = input
self.bitslip_signal = bitslip_signal
self.in_testpattern_mode = in_testpattern_mode
self.ddr_domain = ddr_domain
self.testpattern = testpattern
self.delay = ControlSignal(5, reset=15)
self.error = StatusSignal(32)
self.output = StatusSignal(8)
def __init__(self, pin, ddr_domain, qdr_domain):
self.pin = pin
self.ddr_domain = ddr_domain
self.qdr_domain = qdr_domain
self.not_valid_cnt = StatusSignal(16)
self.blanking_threshold = ControlSignal(
16, reset=(480 * 16)) # 128 is dvi spec, for hdmi this should be 8
self.blankings_hit = StatusSignal(32)
self.raw_word = StatusSignal(10)
self.invert = StatusSignal(reset=1)
self.data = StatusSignal(8)
self.data_enable = StatusSignal()
self.control = StatusSignal(2)
def elaborate(self, platform):
m = Module()
self.invert = ControlSignal(
reset=is_signal_inverted(platform, self.pad))
oserdes = m.submodules.oserdes = _OSerdes(data_width=self.bit_width,
tristate_width=1,
data_rate_oq="ddr",
serdes_mode="master",
data_rate_tq="buf")
m.d.comb += oserdes.oce.eq(1)
m.d.comb += oserdes.clk.eq(ClockSignal(self.ddr_domain))
m.d.comb += oserdes.clkdiv.eq(ClockSignal())
m.d.comb += oserdes.rst.eq(ResetSignal())
m.d.comb += Cat(
oserdes.d[i]
for i in (range(1, 9) if self.msb_first else reversed(range(1, 9))
)).eq(self.value ^ self.invert)
m.d.comb += self.pad.eq(oserdes.oq)
return m
def __init__(self, resource):
self.resource = resource
self.blanking_threshold = ControlSignal(16, reset=(480 * 16))
self.measured_width = StatusSignal(16)
self.measured_height = StatusSignal(16)
self.width = ControlSignal(16, reset=1440)
self.height = ControlSignal(16, reset=480)
self.blank_r = ControlSignal()
self.blank_g = ControlSignal()
self.blank_b = ControlSignal()
self.stable_lines_needed = 2000
self.lines_stable = StatusSignal(range(self.stable_lines_needed + 1))
self.frames_stable = StatusSignal(32)
self.stable = StatusSignal()
self.always_valid = ControlSignal()
self.output_not_ready = StatusSignal(32)
self.output = ImageStream(24)
def __init__(self, input: ImageStream):
self.input = input
self.output = ImageStream(24)
self.shift_x = ControlSignal()
self.shift_y = ControlSignal()
def __init__(self, width, count_if_not_ready=False):
self.output = BasicStream(width, name="counter_stream")
self.count_if_not_ready = ControlSignal(reset=count_if_not_ready)