def test_multiple_interface(self):
# the following calls used to create issues (several interfaces from
# the same device)
ftdi1 = Ftdi()
ftdi1.open(interface=1)
ftdi2 = Ftdi()
ftdi2.open(interface=2)
import time
for x in range(5):
print "If#1: ", hex(ftdi1.poll_modem_status())
print "If#2: ", ftdi2.modem_status()
time.sleep(0.500)
ftdi1.close()
ftdi2.close()
def __init__(self, interface=0, vid=None, pid=None):
"""
Constructor
:param interface: May specify either the serial number or the device
index.
:type interface: string or int
"""
if not have_pyftdi:
raise ImportError(
'The USBDevice class has been disabled due to missing requirement: pyftdi or pyusb.'
)
Device.__init__(self)
self._device = Ftdi()
self._interface = 0
self._device_number = 0
self._serial_number = None
self._vendor_id = USBDevice.DEFAULT_VENDOR_ID
if vid:
self._vendor_id = vid
self._product_id = USBDevice.DEFAULT_PRODUCT_ID
if pid:
self._product_id = pid
self._endpoint = 0
self._description = None
self.interface = interface
def __init__(self, silent_clock=False, cs_count=4):
"""Instanciate a SpiController.
silent_clock should be set to avoid clocking out SCLK when all /CS
signals are released. This clock beat is used to enforce a delay
between /CS signal activation. When weird SPI devices are used,
SCLK beating may cause trouble. In this case, silent_clock should
be set but beware that SCLK line should be fitted with a pull-down
resistor, as SCLK is high-Z during this short period of time.
cs_count is the number of /CS lines (one per device to drive on the
SPI bus)
"""
self._ftdi = Ftdi()
self._cs_bits = ((SpiController.CS_BIT << cs_count) - 1) & \
~(SpiController.CS_BIT - 1)
self._ports = [None] * cs_count
self._direction = self._cs_bits | \
SpiController.DO_BIT | \
SpiController.SCK_BIT
self._cs_high = Array('B')
if silent_clock:
# Set SCLK as input to avoid emitting clock beats
self._cs_high.extend([
Ftdi.SET_BITS_LOW, self._cs_bits,
self._direction & ~SpiController.SCK_BIT
])
# /CS to SCLK delay, use 8 clock cycles as a HW tempo
self._cs_high.extend([Ftdi.WRITE_BITS_TMS_NVE, 8 - 1, 0xff])
# Restore idle state
self._cs_high.extend(
[Ftdi.SET_BITS_LOW, self._cs_bits, self._direction])
self._immediate = Array('B', [Ftdi.SEND_IMMEDIATE])
self._frequency = 0.0
def __init__(self, idVendor=0x0403, idProduct=0x8530, debug = False):
Olympus.__init__(self, debug)
self.vendor = idVendor
self.product = idProduct
self.dev = Ftdi()
self._open_dev()
self.name = "Dionysus"
def __init__(self, idVendor, idProduct, interface):
#all pins are in high impedance
self.vendor = idVendor
self.product = idProduct
self.interface = interface
self.f = Ftdi()
# print "vid: %s, pid: %s" % (str(hex(idVendor)), str(hex(idProduct)))
self.f.open_bitbang(idVendor, idProduct, interface)
def burn(firmware_file):
global f
f = Ftdi()
try:
f.open_mpsse(0x0403,
0x6010,
description="HiSPARC III Master",
interface=1,
initial=1,
direction=0b11)
except (FtdiError, usb.USBError):
print "RESET"
usb.util.dispose_resources(f.usb_dev)
f.open_mpsse(0x0403,
0x6010,
description="HiSPARC III Master",
interface=1,
initial=1,
direction=0b11)
f.write_data([Ftdi.TCK_DIVISOR, 0, 0])
f.write_data([Ftdi.DISABLE_CLK_DIV5])
print_low_bits(f)
print_high_bits(f)
f.write_data([Ftdi.SET_BITS_HIGH, 0, 1])
print_high_bits(f)
f.write_data([Ftdi.SET_BITS_HIGH, 1, 1])
print_high_bits(f)
BUFSIZE = 64 * 1024
with open(os.path.expanduser(firmware_file), 'rb') as file:
while True:
xbuf = file.read(BUFSIZE)
if not xbuf:
break
LENGTH = len(xbuf) - 1
LENGTH_L = LENGTH & 0xff
LENGTH_H = LENGTH >> 8 & 0xff
send_buf = [Ftdi.WRITE_BYTES_PVE_LSB
] + [LENGTH_L, LENGTH_H] + [ord(u) for u in xbuf]
f.write_data(send_buf)
#for i in range(10):
# print_high_bits(f)
# f.write_data([0x8e, 0])
print_high_bits(f)
print_low_bits(f)
def __init__(self, trst=False, frequency=3.0E6):
"""
trst uses the nTRST optional JTAG line to hard-reset the TAP
controller
"""
self._ftdi = Ftdi()
self._trst = trst
self._frequency = frequency
self.direction = JtagController.TCK_BIT | \
JtagController.TDI_BIT | \
JtagController.TMS_BIT | \
(self._trst and JtagController.TRST_BIT or 0)
self._last = None # Last deferred TDO bit
self._write_buff = Array('B')
def __init__(self, silent_clock=False, cs_count=4):
self._ftdi = Ftdi()
self._cs_bits = ((SpiController.CS_BIT << cs_count) - 1) & \
~(SpiController.CS_BIT - 1)
self._ports = [None] * cs_count
self._direction = self._cs_bits | \
SpiController.DO_BIT | \
SpiController.SCK_BIT
self._cs_high = Array('B')
if silent_clock:
# Set SCLK as input to avoid emitting clock beats
self._cs_high.extend([Ftdi.SET_BITS_LOW, self._cs_bits,
self._direction & ~SpiController.SCK_BIT])
# /CS to SCLK delay, use 8 clock cycles as a HW tempo
self._cs_high.extend([Ftdi.WRITE_BITS_TMS_NVE, 8-1, 0xff])
# Restore idle state
self._cs_high.extend([Ftdi.SET_BITS_LOW, self._cs_bits,
self._direction])
self._immediate = Array('B', [Ftdi.SEND_IMMEDIATE])
self._frequency = 0.0
def __init__(self, name, serial=None, channel='A0', numdacs=3, delay=1e-3):
'''
discover and initialize Tunnel_DAC hardware
Input:
serial - serial number of the FTDI converter
channel - 2 character channel id the DAC is connected to;
the first byte identifies the channel (A..D for current devices)
the second byte identifies the bit within that channel (0..7)
numdacs - number of DACs daisy-chained on that line
delay - communications delay assumed between PC and the USB converter
'''
logging.info(__name__ + ': Initializing instrument Tunnel_DAC')
Instrument.__init__(self, name, tags=['physical'])
self._conn = Ftdi()
# VIDs and PIDs of converters used
vps = [
(0x0403, 0x6011), # FTDI UM4232H 4ch
(0x0403, 0x6014) # FTDI UM232H 1ch
]
# explicitly clear device cache of UsbTools
#UsbTools.USBDEVICES = []
# find all devices and obtain serial numbers
devs = self._conn.find_all(vps)
# filter list by serial number if provided
if (serial != None):
devs = [dev for dev in devs if dev[2] == serial]
if (len(devs) == 0):
logging.error(__name__ + ': failed to find matching FTDI devices.')
elif (len(devs) > 1):
logging.error(
__name__ +
': more than one converter found and no serial number given.')
logging.info(__name__ + ': available devices are: %s.' %
str([dev[2] for dev in devs]))
vid, pid, self._serial, channels, description = devs[0]
# parse channel string
if (len(channel) != 2):
logging.error(
__name__ +
': channel identifier must be a string of length 2. ex. A0, D5.'
)
self._channel = 1 + ord(channel[0]) - ord('A')
self._bit = ord(channel[1]) - ord('0')
if ((self._channel < 1) or (self._channel > channels)):
logging.error(__name__ +
': channel %c is not supported by this device.' %
(chr(ord('A') + self._channel - 1)))
if ((self._bit < 0) or (self._bit > 7)):
logging.error(__name__ +
': subchannel must be between 0 and 7, not %d.' %
self._bit)
# open device
self._conn.open(vid, pid, interface=self._channel, serial=self._serial)
logging.info(__name__ +
': using converter with serial #%s' % self._serial)
self._conn.set_bitmode(0xFF, Ftdi.BITMODE_BITBANG)
# 80k generates bit durations of 12.5us, 80 is magic :(
# magic?: 4 from incorrect BITBANG handling of pyftdi, 2.5 from 120MHz instead of 48MHz clock of H devices
# original matlab code uses 19kS/s
self._conn.set_baudrate(19000 / 80)
# house keeping
self._numdacs = numdacs
self._sleeptime = (
10. + 16. * self._numdacs
) * 12.5e-6 + delay # 1st term from hardware parameters, 2nd term from USB
self._minval = -5000.
self._maxval = 5000.
self._resolution = 16 # DAC resolution in bits
self._voltages = [0.] * numdacs
self.add_parameter('voltage',
type=types.FloatType,
flags=Instrument.FLAG_SET,
channels=(1, self._numdacs),
minval=self._minval,
maxval=self._maxval,
units='mV',
format='%.02f') # tags=['sweep']
self.add_function('set_voltages')
self.add_function('commit')
def __init__(self, idVendor, idProduct):
self.vendor = idVendor
self.product = idProduct
self.f = Ftdi()
