def main(architecture):
# architecture = '148'
dfg = parser('dotfiles/Architecture_latency_{}.dot'.format(architecture))
simplified_dfg = parser(
'dotfiles/Architecture_latency_{}_schematic.dot'.format(architecture))
fus: List[AGraph] = dfg.subgraphs()
subgraphs = {}
for subgraph in fus:
subgraphs[subgraph.graph_attr['label'].strip()] = subgraph
for fu in fus:
ATMI.max_cycle = 0
assembler = Assembler()
label = fu.graph_attr['label'].strip()
# NOTE: handle load FUs
if 'load' in label or 'store' in label:
continue
input_map, max_fu = input_mapper.map_input(fu, subgraphs,
simplified_dfg)
rf_alloc_path = 'dotfiles/Architecture_latency_{}_'.format(
architecture) + label + '_rf_allocation.csv'
rf_allocs, max_address = rf_alloc_parser(rf_alloc_path)
assembler.add_assembly(
op_generator.gen_op_insts(rf_allocs, dfg, fu, input_map))
assembler.add_assembly(
alloc_generator.gen_alloc_insts(rf_allocs, dfg, fu, input_map))
try:
assembler.compile(max_address, max_fu)
config = control_signal_generator.gen_config(
assembler, max_address, max_fu, 1, label)
vhdl, tot_wait = control_signal_generator.insert_signals(
assembler.export())
with open('out/' + label + '.program', 'w') as f:
f.write('TOTAL_WAIT_NS ' + str(tot_wait) + '\n')
for line in config:
f.write(line + '\n')
f.write('\n')
for line in vhdl:
f.write(line + '\n')
except MergeException as merge:
print("ERROR COMPILING INSTRUCTIONS FOR " + label + " : " +
merge.args[0])
