#
# Target: Verify verilog code
#
vout = env.IVerilog(TARGET, src_synth)
target_verify = env.Alias('verify', vout)
AlwaysBuild(target_verify)
#
# Target: Simulate testbench
#
sout = env.IVerilog(TARGET_SIM, src_sim)
vcd_file = env.VCD(sout)
target_sim = env.Alias(
'sim', vcd_file,
'gtkwave {0} {1}.gtkw'.format(vcd_file[0],
join(env['PROJECTSRC_DIR'], SIMULNAME)))
AlwaysBuild(target_sim)
#
# Setup default targets
#
Default([binf])
#
# Target: Clean generated files
#
if GetOption('clean'):
env.Default([t, vout, sout, vcd_file])
# -------------------- Simulation ------------------
# -- Constructor para generar simulacion: icarus Verilog
iverilog = Builder(action='iverilog -o $TARGET $SOURCES ',
suffix='.out',
src_suffix='.v')
vcd = Builder(action=' $SOURCE', suffix='.vcd', src_suffix='.out')
simenv = Environment(BUILDERS={
'IVerilog': iverilog,
'VCD': vcd
},
ENV=os.environ)
out = simenv.IVerilog(TARGET_SIM, src_sim)
vcd_file = simenv.VCD(SIMULNAME, out)
waves = simenv.Alias(
'sim', vcd_file,
'gtkwave ' + join(env['PROJECT_DIR'], "%s " % vcd_file[0]) +
join(env['PROJECTSRC_DIR'], SIMULNAME) + '.gtkw')
AlwaysBuild(waves)
Default([binf])
# -- These is for cleaning the files generated using the alias targets
if GetOption('clean'):
env.Default([t])
simenv.Default([out, vcd_file])
