def __init__(self, platform):
clk_freq = int((1/(platform.default_clk_period))*1000000000)
SoCCore.__init__(self, platform, clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Litescope example design",
with_timer=False
)
self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
self.submodules.inout = LiteScopeInOut(8)
for i in range(8):
try:
self.comb += platform.request("user_led", i).eq(self.inout.o[i])
except:
pass
counter = Signal(16)
self.sync += counter.eq(counter + 1)
self.debug = (counter)
self.submodules.logic_analyzer = LiteScopeLogicAnalyzer(self.debug, 512, with_rle=True, with_subsampler=True)
self.logic_analyzer.trigger.add_port(LiteScopeTerm(self.logic_analyzer.dw))
def __init__(self, platform):
clk_freq = int((1 / (platform.default_clk_period)) * 1000000000)
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="LiteUSB example design",
with_timer=False)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
self.submodules.usb_phy = FT245PHY(platform.request("usb_fifo"),
self.clk_freq)
self.submodules.usb_core = LiteUSBCore(self.usb_phy,
self.clk_freq,
with_crc=False)
# Wishbone Bridge
usb_bridge_port = self.usb_core.crossbar.get_port(
self.usb_map["bridge"])
self.add_cpu_or_bridge(
LiteUSBWishboneBridge(usb_bridge_port, self.clk_freq))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# Leds
leds = Cat(iter([platform.request("user_led", i) for i in range(8)]))
self.submodules.leds = GPIOOut(leds)
def __init__(self, platform):
sys_clk_freq = int(100e6)
SoCCore.__init__(self, platform, sys_clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Fast scope", ident_version=True,
with_timer=False
)
self.submodules.serdes = SerdesIO(platform)
# crg
self.submodules.crg = _CRG(platform,sys_clk_freq)
# bridge
bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=115200)
self.submodules.bridge = bridge
self.add_wb_master(bridge.wishbone)
# Litescope Analyzer
analyzer_groups = {}
# Analyzer group
analyzer_groups[0] = [
self.serdes.d0.signals,
self.serdes.d1.signals,
self.serdes.d2.signals,
self.serdes.d3.signals,
]
# analyzer
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 512)
def __init__(self, platform):
clk_freq = int((1/(platform.default_clk_period))*1000000000)
SoCCore.__init__(self, platform, clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Litescope example design",
with_timer=False
)
self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
self.submodules.io = LiteScopeIO(8)
for i in range(8):
try:
self.comb += platform.request("user_led", i).eq(self.io.output[i])
except:
pass
counter = Signal(16)
self.sync += counter.eq(counter + 1)
toto = Signal()
self.submodules.analyzer = LiteScopeAnalyzer(counter, 512)
def __init__(self,
sys_clk_freq=int(50e6),
revision="revd",
sdram_rate="1:2",
mister_sdram=None,
**kwargs):
platform = arrow_sockit.Platform(revision)
# Defaults to UART over JTAG because serial is attached to the HPS and cannot be used.
if kwargs["uart_name"] == "serial":
kwargs["uart_name"] = "jtag_atlantic"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on the Arrow SoCKit",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_sdram=mister_sdram != None,
sdram_rate=sdram_rate)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
if mister_sdram == "xs_v22":
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=W9825G6KH6(sys_clk_freq, sdram_rate),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
if mister_sdram == "xs_v24":
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=AS4C32M16(sys_clk_freq, sdram_rate),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
def __init__(self, platform):
sys_clk_freq = int((1e9 / platform.default_clk_period))
SoCCore.__init__(self,
platform,
sys_clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Litescope example design",
ident_version=True,
with_timer=False)
# crg
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# bridge
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# Litescope IO
self.submodules.io = LiteScopeIO(8)
for i in range(8):
try:
self.comb += platform.request("user_led",
i).eq(self.io.output[i])
except:
pass
# Litescope Analyzer
analyzer_groups = {}
# counter group
counter = Signal(16, name_override="counter")
zero = Signal(name_override="zero")
self.sync += counter.eq(counter + 1)
self.comb += zero.eq(counter == 0)
analyzer_groups[0] = [zero, counter]
# communication group
analyzer_groups[1] = [
platform.lookup_request("serial").tx,
platform.lookup_request("serial").rx, self.cpu_or_bridge.wishbone
]
# fsm group
fsm = FSM(reset_state="STATE1")
self.submodules += fsm
fsm.act("STATE1", NextState("STATE2"))
fsm.act("STATE2", NextState("STATE1"))
analyzer_groups[2] = [fsm]
# analyzer
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 512)
def __init__(self,
platform,
clk_freq=int(166e6),
mac_address=0x10e2d5000000,
ip_address="192.168.1.50"):
sys_clk_freq = int((1 / (platform.default_clk_period)) * 1e9)
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="LiteEth Base Design",
with_timer=False)
# Serial Wishbone Bridge
serial_bridge = UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200)
self.submodules += serial_bridge
self.add_wb_master(serial_bridge.wishbone)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# Wishbone SRAM (to test Wishbone over UART and Etherbone)
self.submodules.sram = wishbone.SRAM(1024)
self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus)
# Ethernet PHY and UDP/IP stack
self.submodules.ethphy = ethphy = LiteEthPHY(
clock_pads=platform.request("eth_clocks"),
pads=platform.request("eth"),
clk_freq=clk_freq)
self.add_csr("ethphy")
self.submodules.ethcore = ethcore = LiteEthUDPIPCore(
phy=ethphy,
mac_address=mac_address,
ip_address=ip_address,
clk_freq=clk_freq)
self.add_csr("ethcore")
if isinstance(platform.toolchain, XilinxVivadoToolchain):
self.crg.cd_sys.clk.attr.add("keep")
ethphy.crg.cd_eth_rx.clk.attr.add("keep")
ethphy.crg.cd_eth_tx.clk.attr.add("keep")
platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 125e6)
platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 125e6)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
ethphy.crg.cd_eth_rx.clk,
ethphy.crg.cd_eth_tx.clk)
def __init__(self,
sys_clk_freq=int(50e6),
integrated_rom_size=0x8000,
**kwargs):
platform = arty.Platform()
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
integrated_sram_size=0x8000,
ident="MiniLitex",
cpu_variant="lite",
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
def __init__(self,
platform,
clk_freq=166 * 1000000,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50"):
clk_freq = int((1 / (platform.default_clk_period)) * 1000000000)
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="LiteEth Base Design",
with_timer=False)
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# wishbone SRAM (to test Wishbone over UART and Etherbone)
self.submodules.sram = wishbone.SRAM(1024)
self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus)
# ethernet PHY and UDP/IP stack
self.submodules.phy = LiteEthPHY(platform.request("eth_clocks"),
platform.request("eth"),
clk_freq=clk_freq)
self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address,
convert_ip(ip_address),
clk_freq)
if isinstance(platform.toolchain, XilinxVivadoToolchain):
self.specials += [
Keep(self.crg.cd_sys.clk),
Keep(self.phy.crg.cd_eth_rx.clk),
Keep(self.phy.crg.cd_eth_tx.clk)
]
platform.add_platform_command("""
create_clock -name sys_clk -period 6.0 [get_nets sys_clk]
create_clock -name eth_rx_clk -period 8.0 [get_nets eth_rx_clk]
create_clock -name eth_tx_clk -period 8.0 [get_nets eth_tx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_rx_clk]
set_false_path -from [get_clocks eth_rx_clk] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_tx_clk]
set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk]
""")
def __init__(self,
toolchain="vivado",
sys_clk_freq=int(60e6),
with_ethernet=False,
with_ram=False,
board_variant="a7-35",
**kwargs):
platform = arty.Platform(variant=board_variant, toolchain=toolchain)
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Arty A7",
ident_version=False,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq, toolchain)
# DDR3 SDRAM -------------------------------------------------------------------------------
if with_ram:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
if with_ethernet:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self, platform, revision="sata_gen3", trx_dw=16, with_bist_robustness=False):
clk_freq = 200*1000000
SoCCore.__init__(self, platform, clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="LiteSATA example design",
with_timer=False)
self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform)
# SATA PHY/Core/Frontend
self.submodules.sata_phy = LiteSATAPHY(platform.device,
platform.request("sata_clocks"),
platform.request("sata", 0),
revision,
clk_freq,
trx_dw)
self.submodules.sata_core = LiteSATACore(self.sata_phy)
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
if with_bist_robustness:
sata_bist = LiteSATABISTRobustness(self.sata_crossbar)
self.submodules.sata_bist = LiteSATABISTRobustnessCSR(sata_bist)
else:
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar, with_csr=True)
# Status Leds
self.submodules.leds = StatusLeds(platform, self.sata_phy)
self.specials += [
Keep(ClockSignal("sata_rx")),
Keep(ClockSignal("sata_tx"))
]
platform.add_platform_command("""
create_clock -name sys_clk -period 5 [get_nets sys_clk]
create_clock -name sata_rx_clk -period {sata_clk_period} [get_nets sata_rx_clk]
create_clock -name sata_tx_clk -period {sata_clk_period} [get_nets sata_tx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]
set_false_path -from [get_clocks sata_rx_clk] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
""".format(sata_clk_period="3.3" if trx_dw == 16 else "6.6"))
def __init__(self, platform, revision="sata_gen2", data_width=16):
sys_clk_freq = int(100e6)
SoCCore.__init__(self,
platform,
sys_clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="LiteSATA example design",
ident_version=True,
with_timer=False)
self.add_cpu(
UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu.wishbone)
self.submodules.crg = CRG(platform)
# SATA PHY/Core/Frontend
self.submodules.sata_phy = LiteSATAPHY(platform.device,
platform.request("sata_clocks"),
platform.request("sata",
0), revision,
sys_clk_freq, data_width)
self.submodules.sata_core = LiteSATACore(self.sata_phy)
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar,
with_csr=True)
# Status Leds
self.submodules.leds = StatusLeds(platform, self.sata_phy)
self.sata_phy.crg.cd_sata_rx.clk.attr.add("keep")
self.sata_phy.crg.cd_sata_tx.clk.attr.add("keep")
platform.add_platform_command("""
create_clock -name sys_clk -period 10 [get_nets sys_clk]
create_clock -name sata_rx_clk -period {sata_clk_period} [get_nets sata_rx_clk]
create_clock -name sata_tx_clk -period {sata_clk_period} [get_nets sata_tx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]
set_false_path -from [get_clocks sata_rx_clk] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
""".format(sata_clk_period="6.6" if data_width == 16 else "13.2"))
def __init__(self, platform, revision="sata_gen3", trx_dw=16):
clk_freq = 200 * 1000000
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="LiteSATA example design",
with_timer=False)
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform)
# SATA PHY/Core/Frontend
self.submodules.sata_phy = LiteSATAPHY(platform.device,
platform.request("sata_clocks"),
platform.request("sata", 0),
revision, clk_freq, trx_dw)
self.submodules.sata_core = LiteSATACore(self.sata_phy)
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar,
with_csr=True)
# Status Leds
self.submodules.leds = StatusLeds(platform, self.sata_phy)
self.specials += [
Keep(ClockSignal("sata_rx")),
Keep(ClockSignal("sata_tx"))
]
platform.add_platform_command("""
create_clock -name sys_clk -period 5 [get_nets sys_clk]
create_clock -name sata_rx_clk -period {sata_clk_period} [get_nets sata_rx_clk]
create_clock -name sata_tx_clk -period {sata_clk_period} [get_nets sata_tx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]
set_false_path -from [get_clocks sata_rx_clk] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
""".format(sata_clk_period="3.3" if trx_dw == 16 else "6.6"))
def __init__(self, platform, with_uart_bridge=True):
sys_clk_freq = int(125e6)
SoCCore.__init__(self,
platform,
sys_clk_freq,
cpu_type=None,
shadow_base=0x00000000,
csr_data_width=32,
with_uart=False,
ident="LitePCIe example design",
ident_version=True,
with_timer=False)
self.submodules.crg = _CRG(platform)
# PCIe endpoint
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x1"))
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy,
with_reordering=True)
# PCIe Wishbone bridge
self.add_cpu_or_bridge(
LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# PCIe DMA
self.submodules.dma = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_loopback=True)
if with_uart_bridge:
self.submodules.uart_bridge = UARTWishboneBridge(
platform.request("serial"), sys_clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
# MSI
self.submodules.msi = LitePCIeMSI()
self.comb += self.msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"DMA_WRITER": self.dma.writer.irq,
"DMA_READER": self.dma.reader.irq
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
def __init__(self, platform):
clk_freq = int((1 / (platform.default_clk_period)) * 1000000000)
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Litescope example design",
with_timer=False)
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
self.submodules.io = LiteScopeIO(8)
for i in range(8):
try:
self.comb += platform.request("user_led",
i).eq(self.io.output[i])
except:
pass
# use name override to keep naming in capture
counter = Signal(4, name_override="counter")
counter0 = Signal(name_override="counter0")
counter1 = Signal(name_override="counter1")
counter2 = Signal(name_override="counter2")
counter3 = Signal(name_override="counter3")
self.sync += counter.eq(counter + 1)
self.comb += [
counter0.eq(counter[0]),
counter1.eq(counter[1]),
counter2.eq(counter[2]),
counter3.eq(counter[3]),
]
# group for vcd capture
vcd_group = [counter]
# group for sigrok capture (no bus support)
sigrok_group = [counter0, counter1, counter2, counter3]
analyzer_signals = {0: vcd_group, 1: sigrok_group}
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
def __init__(self, platform, clk_freq=100*1000000):
self.clock_domains.cd_sys = ClockDomain("sys")
self.comb += [
self.cd_sys.clk.eq(platform.request("sys_clock")),
self.cd_sys.rst.eq(platform.request("sys_reset"))
]
SoCCore.__init__(self, platform, clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Litescope example design",
with_timer=False
)
self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu.wishbone)
self.bus = platform.request("bus")
self.submodules.analyzer = LiteScopeAnalyzer((self.bus), 512)
def __init__(self, sys_clk_freq, **kwargs):
platform = Platform()
kwargs["cpu_type"] = None
kwargs["with_uart"] = False
kwargs["with_timer"] = False
kwargs["with_ctrl"] = True
# We don't have RAM or ROM
kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0
kwargs["csr_data_width"] = 32
SoCCore.__init__(self, platform, sys_clk_freq, **kwargs)
self.submodules.crg = CRG(platform, sys_clk_freq)
# SPI to wishbone bridge
spi_pads = platform.request("spi_slave")
self.submodules.bridge = SPIBridge(spi_pads)
self.bus.add_master(name="bridge", master=self.bridge.wishbone)
ps2_ext = [(
"ps2",
0,
Subsignal("dat", Pins("25"), IOStandard("LVCMOS33")), # PB1
Subsignal("clk", Pins("26"), IOStandard("LVCMOS33")), # PB0
)]
platform.add_extension(ps2_ext)
ps2 = platform.request("ps2")
self.submodules.ps2 = PS2Controller(ps2.dat, ps2.clk, sys_clk_freq)
self.add_csr("ps2")
if hasattr(self.cpu, "interrupt"):
self.add_interrupt("ps2")
irq = platform.request("irq")
self.sync += irq.eq(self.ps2.ev.irq)
# Suppress yosys output
assert hasattr(self.platform.toolchain, "build_template")
if self.platform.toolchain.build_template[0].startswith("yosys "):
self.platform.toolchain.build_template[0] =\
self.platform.toolchain.build_template[0].replace("yosys ", "yosys -q ")
def __init__(self, platform, clk_freq=100*1000000):
self.clock_domains.cd_sys = ClockDomain("sys")
self.comb += [
self.cd_sys.clk.eq(platform.request("sys_clock")),
self.cd_sys.rst.eq(platform.request("sys_reset"))
]
SoCCore.__init__(self, platform, clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Litescope example design",
with_timer=False
)
self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.bus = platform.request("bus")
self.submodules.logic_analyzer = LiteScopeLogicAnalyzer((self.bus), 512, with_rle=True, with_subsampler=True)
self.logic_analyzer.trigger.add_port(LiteScopeTerm(self.logic_analyzer.dw))
def __init__(self, platform, cpu, sim: bool, **kwargs):
sys_clk_freq = int(1e9 / platform.default_clk_period)
kwargs['with_uart'] = not sim
SoCCore.__init__(self, platform,
cpu_type=cpu.name,
clk_freq=sys_clk_freq,
**kwargs)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
self.submodules.gpio_led = gpio.GPIOOut(platform.request("user_led"))
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map['main_ram'])
if sim:
# Serial -----------------------------------------------------------------------------------
self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial"))
self.submodules.uart = uart.UART(self.uart_phy,
tx_fifo_depth=kwargs["uart_fifo_depth"],
rx_fifo_depth=kwargs["uart_fifo_depth"])
self.add_csr("uart")
self.add_interrupt("uart")
def __init__(self, platform, with_uart_bridge=True):
clk_freq = 125 * 1000000
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
shadow_base=0x00000000,
csr_data_width=32,
with_uart=False,
ident="LitePCIe example design",
with_timer=False)
self.submodules.crg = _CRG(platform)
# PCIe endpoint
self.submodules.pcie_phy = S7PCIEPHY(platform, link_width=2)
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy,
with_reordering=True)
# PCIe Wishbone bridge
self.add_cpu_or_bridge(
LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# PCIe DMA
self.submodules.dma = LitePCIeDMA(self.pcie_phy,
self.pcie_endpoint,
with_loopback=True)
self.dma.source.connect(self.dma.sink)
if with_uart_bridge:
self.submodules.uart_bridge = UARTWishboneBridge(
platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
# MSI
self.submodules.msi = LitePCIeMSI()
self.comb += self.msi.source.connect(self.pcie_phy.interrupt)
self.interrupts = {
"dma_writer": self.dma.writer.irq,
"dma_reader": self.dma.reader.irq
}
for k, v in sorted(self.interrupts.items()):
self.comb += self.msi.irqs[self.interrupt_map[k]].eq(v)
def __init__(self, platform, clk_freq=int(100e6)):
self.clock_domains.cd_sys = ClockDomain("sys")
self.comb += [
self.cd_sys.clk.eq(platform.request("clock")),
self.cd_sys.rst.eq(platform.request("reset"))
]
SoCCore.__init__(self, platform, clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
with_timer=False
)
self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=3000000))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.analyzer = LiteScopeAnalyzer(platform.request("bus"), 512)
self.submodules.io = LiteScopeIO(16)
self.comb += [
self.io.input.eq(platform.request("i")),
platform.request("o").eq(self.io.output),
]
def __init__(self, platform):
# Initialize SoC things
SoCCore.__init__(self,
platform,
SYS_CLK,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="csrdemo",
ident_version=True,
with_timer=False)
# Create a Wishbone bus, bridged to the UART
bridge = UARTWishboneBridge(platform.request("serial"),
SYS_CLK,
baudrate=115200)
self.submodules.bridge = bridge
self.add_wb_master(bridge.wishbone)
# Then wire up the addition
self.submodules.adder = Adder()
self.add_csr("adder")
def __init__(self, sys_clk_freq=int(50e6), revision="revd", **kwargs):
platform = arrow_sockit.Platform(revision)
# Defaults to Crossover UART because serial is attached to the HPS and cannot be used.
if kwargs["uart_name"] == "serial":
kwargs["uart_name"] = "crossover"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on the Arrow SoCKit",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self, platform, clk_freq=166*1000000,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50"):
clk_freq = int((1/(platform.default_clk_period))*1000000000)
SoCCore.__init__(self, platform, clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="LiteEth Base Design",
with_timer=False
)
self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# wishbone SRAM (to test Wishbone over UART and Etherbone)
self.submodules.sram = wishbone.SRAM(1024)
self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus)
# ethernet PHY and UDP/IP stack
self.submodules.phy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=clk_freq)
self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address, convert_ip(ip_address), clk_freq)
if isinstance(platform.toolchain, XilinxVivadoToolchain):
self.specials += [
Keep(self.crg.cd_sys.clk),
Keep(self.phy.crg.cd_eth_rx.clk),
Keep(self.phy.crg.cd_eth_tx.clk)
]
platform.add_platform_command("""
create_clock -name sys_clk -period 6.0 [get_nets sys_clk]
create_clock -name eth_rx_clk -period 8.0 [get_nets eth_rx_clk]
create_clock -name eth_tx_clk -period 8.0 [get_nets eth_tx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_rx_clk]
set_false_path -from [get_clocks eth_rx_clk] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_tx_clk]
set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk]
""")
def __init__(self, platform):
clk_freq = int((1/(platform.default_clk_period))*1000000000)
SoCCore.__init__(self, platform, clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="LiteUSB example design",
with_timer=False
)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
self.submodules.usb_phy = FT245PHY(platform.request("usb_fifo"), self.clk_freq)
self.submodules.usb_core = LiteUSBCore(self.usb_phy, self.clk_freq, with_crc=False)
# Wishbone Bridge
usb_bridge_port = self.usb_core.crossbar.get_port(self.usb_map["bridge"])
self.add_cpu_or_bridge(LiteUSBWishboneBridge(usb_bridge_port, self.clk_freq))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# Leds
leds = Cat(iter([platform.request("user_led", i) for i in range(8)]))
self.submodules.leds = GPIOOut(leds)
def __init__(self, platform, with_uart_bridge=True):
clk_freq = 125*1000000
SoCCore.__init__(self, platform, clk_freq,
cpu_type=None,
shadow_base=0x00000000,
csr_data_width=32,
with_uart=False,
ident="LitePCIe example design",
with_timer=False
)
self.submodules.crg = _CRG(platform)
# PCIe endpoint
self.submodules.pcie_phy = S7PCIEPHY(platform, link_width=2)
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True)
# PCIe Wishbone bridge
self.add_cpu_or_bridge(LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# PCIe DMA
self.submodules.dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True)
self.dma.source.connect(self.dma.sink)
if with_uart_bridge:
self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
# MSI
self.submodules.msi = LitePCIeMSI()
self.comb += self.msi.source.connect(self.pcie_phy.interrupt)
self.interrupts = {
"dma_writer": self.dma.writer.irq,
"dma_reader": self.dma.reader.irq
}
for k, v in sorted(self.interrupts.items()):
self.comb += self.msi.irqs[self.interrupt_map[k]].eq(v)
def __init__(self,
debug,
flash_offset,
board,
revision,
with_ethernet=False,
with_etherbone=False,
eth_phy=0,
sys_clk_freq=60e6,
use_internal_osc=False,
sdram_rate="1:1",
**kwargs):
"""Create a basic SoC for Colorlight 5A-75X.
Returns:
Newly-constructed SoC
"""
board = board.lower()
assert board in ["5a-75b", "5a-75e"]
if board == "5a-75b":
platform = colorlight_5a_75b.Platform(revision=revision)
elif board == "5a-75e":
platform = colorlight_5a_75e.Platform(revision=revision)
if board == "5a-75e" and revision == "6.0" and (with_etherbone
or with_ethernet):
assert use_internal_osc, "You cannot use the 25MHz clock as system clock since it is provided by the Ethernet PHY and will stop during PHY reset."
# Set cpu name and variant defaults when none are provided
if "cpu_variant" not in kwargs:
if debug:
kwargs["cpu_variant"] = "imac+debug"
else:
kwargs["cpu_variant"] = "imac"
kwargs["integrated_main_ram_size"] = 0
kwargs["integrated_rom_size"] = 0
kwargs["csr_data_width"] = 32
# Set CPU reset address
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + flash_offset
# Select "crossover" as soc uart instead of "serial"
# We have to make that selection before calling the parent initializer
if debug:
kwargs["uart_name"] = "crossover"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
int(sys_clk_freq),
ident="LiteX SoC on Colorlight " + board.upper(),
ident_version=True,
**kwargs)
with_rst = kwargs["uart_name"] not in [
"serial", "bridge", "crossover"
] # serial_rx shared with user_btn_n.
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
self.submodules.crg = _CRG(platform,
sys_clk_freq,
use_internal_osc=use_internal_osc,
with_usb_pll=with_usb_pll,
with_rst=with_rst,
sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
if board == "5a-75e" and revision == "6.0":
sdram_cls = M12L64322A
sdram_size = 0x80000000
else:
sdram_cls = M12L16161A
sdram_size = 0x40000000
self.add_sdram("sdram",
phy=self.sdrphy,
module=sdram_cls(sys_clk_freq, sdram_rate),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", sdram_size),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
# for doing writes.
spiflash_size = 32 * 1024 * 1024
self.submodules.spiflash = spiflash = SpiFlash(
platform.request("spiflash"), dummy=8, endianness="little")
spiflash.add_clk_primitive(platform.device)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=spiflash_size)
self.add_csr("spiflash")
# Add ROM linker region
self.add_memory_region("rom",
self.mem_map["spiflash"] + flash_offset,
spiflash_size - flash_offset,
type="cached+linker")
# In debug mode, add a UART bridge. This takes over from the normal UART bridge,
# however you can use the "crossover" UART to communicate with this over the bridge.
if debug:
self.submodules.uart_bridge = UARTWishboneBridge(
platform.request("serial"), sys_clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
if hasattr(self, "cpu") and self.cpu.name == "vexriscv":
self.register_mem("vexriscv_debug", 0xf00f0000,
self.cpu.debug_bus, 0x100)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks", eth_phy),
pads=self.platform.request("eth", eth_phy))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
def __init__(self, platform,
use_dsp=False, placer="heap", output_dir="build",
pnr_seed=0, sim=False,
**kwargs):
self.output_dir = output_dir
clk_freq = int(sysclkfreq)
# Core -------------------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq,
integrated_sram_size=0,
uart_name="crossover",
cpu_reset_address=self.mem_map["spiflash"]+GATEWARE_SIZE,
csr_data_width=32, **kwargs) # with_uart=False
self.submodules.crg = platform.CRG(platform)
self.add_csr("crg")
# Version ----------------------------------------------------------------------------------------
self.submodules.git = GitInfo()
self.add_csr("git")
# Power management -------------------------------------------------------------------------------
# Betrusted Power management interface
self.submodules.power = BtPower(platform.request("power"))
self.add_csr("power")
# Keyboard power-on + debug mux ------------------------------------------------------------------
# Use to debug bootstrapping issues, avoid internal state on SoC messing with access to UART pads.
# Prevents sleep/wake from working due to loss of modal pinmux.
debugonly = False
if debugonly:
self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
if hasattr(self, "cpu"):
os.path.join(output_dir, "gateware")
self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x100)
else:
serialpads = platform.request("serial")
dbguart_tx = Signal()
dbguart_rx = Signal()
dbgpads = Record([('rx', 1), ('tx', 1)], name="serial")
dbgpads.rx = dbguart_rx
dbgpads.tx = dbguart_tx
# serialpad RX needs to drive a scan signal so we can detect it on the other side of the matrix
keycol0_ts = TSTriple(1)
self.specials += keycol0_ts.get_tristate(serialpads.rx)
#self.comb += serialpads.rx.eq(1)
self.comb += dbgpads.rx.eq(keycol0_ts.i)
self.comb += self.power.mon1.eq(platform.request("up5k_keyrow1"))
self.comb += self.power.mon0.eq(platform.request("up5k_keyrow0"))
# serialpad TX is what we use to test for keyboard hit to power on the SOC
# only allow test keyboard hit patterns when the SOC is powered off
self.comb += serialpads.tx.eq( (~self.power.soc_on & self.power.power.fields.kbddrive) | (self.power.soc_on & dbgpads.tx) )
self.comb += keycol0_ts.oe.eq( ~self.power.soc_on & self.power.power.fields.kbddrive ) # force signal on the rx pin when in power off & scan
self.comb += keycol0_ts.o.eq(1) # drive a '1' for scan
# Debug block ------------------------------------------------------------------------------------
self.submodules.uart_bridge = UARTWishboneBridge(dbgpads, clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
if hasattr(self, "cpu"):
os.path.join(output_dir, "gateware")
self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x100)
# RAM/ROM/reset cluster --------------------------------------------------------------------------
spram_size = 128*1024
self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus, spram_size)
# Add a simple bit-banged SPI Flash module
spi_pads = platform.request("spiflash")
self.submodules.picorvspi = PicoRVSpi(platform, spi_pads)
self.register_mem("spiflash", self.mem_map["spiflash"],
self.picorvspi.bus, size=SPI_FLASH_SIZE)
self.add_csr("picorvspi")
# I2C --------------------------------------------------------------------------------------------
self.submodules.i2c = HardI2C(platform, platform.request("i2c", 0))
self.add_wb_slave(self.mem_map["i2c"], self.i2c.bus, 16*4)
self.add_memory_region("i2c", self.mem_map["i2c"], 16*4, type='io')
self.add_csr("i2c")
self.add_interrupt("i2c")
# High-resolution tick timer ---------------------------------------------------------------------
self.submodules.ticktimer = TickTimer(1000, clk_freq, bits=40)
self.add_csr("ticktimer")
self.add_interrupt("ticktimer")
# COM port (spi peripheral to Artix) ------------------------------------------------------------------
# FIXME: we should have these RTL blocks come from a deps/gateware submodule, not rtl. This way sims are consistent with implementation
self.submodules.com = SpiFifoPeripheral(platform.request("com"))
self.add_wb_slave(self.mem_map["com"], self.com.bus, 4)
self.add_memory_region("com", self.mem_map["com"], 4, type='io')
self.add_csr("com")
self.add_interrupt("com")
self.comb += self.com.oe.eq(self.power.stats.fields.state) # only drive to FPGA when it's powered up
# SPI port to wifi (controller) ------------------------------------------------------------------
self.submodules.wifi = ClockDomainsRenamer({'spi':'sys'})(SpiController(platform.request("wifi"), gpio_cs=True)) # control CS with GPIO per wf200 API spec
self.add_csr("wifi")
self.add_interrupt("wifi")
#### Platform config & build below ---------------------------------------------------------------
# Override default LiteX's yosys/build templates
assert hasattr(platform.toolchain, "yosys_template")
assert hasattr(platform.toolchain, "build_template")
platform.toolchain.yosys_template = [
"{read_files}",
"attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
"synth_ice40 -json {build_name}.json -top {build_name}",
]
platform.toolchain.build_template = [
"yosys -q -l {build_name}.rpt {build_name}.ys",
"nextpnr-ice40 --json {build_name}.json --pcf {build_name}.pcf --asc {build_name}.txt \
--pre-pack {build_name}_pre_pack.py --{architecture} --package {package}",
"icepack {build_name}.txt {build_name}.bin"
]
# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
# The "-reult" adds an additional LUT pass to pack more stuff in,
# and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
# This increases density, and lets us use the FPGA more efficiently.
platform.toolchain.yosys_template[2] += " -relut -abc2 -dffe_min_ce_use 4 -relut"
if use_dsp:
platform.toolchain.yosys_template[2] += " -dsp"
# Disable final deep-sleep power down so firmware words are loaded
# onto softcore's address bus.
platform.toolchain.build_template[2] = "icepack -s {build_name}.txt {build_name}.bin"
# Allow us to set the nextpnr seed
platform.toolchain.build_template[1] += " --seed " + str(pnr_seed)
if placer is not None:
platform.toolchain.build_template[1] += " --placer {}".format(placer)
# Allow loops for RNG placement
platform.toolchain.build_template[1] += " --ignore-loops"
if sim:
class _WishboneBridge(Module):
def __init__(self, interface):
self.wishbone = interface
self.add_cpu(_WishboneBridge(self.platform.request("wishbone")))
self.add_wb_master(self.cpu.wishbone)
def __init__(self,
*,
args,
sys_clk_freq,
sdram_module_cls,
sdram_module_speedgrade=None,
sdram_module_spd_file=None,
ip_address="192.168.100.50",
mac_address=0x10e2d5000001,
udp_port=1234,
**kwargs):
self.args = args
self.sys_clk_freq = sys_clk_freq
self.ip_address = ip_address
self.mac_address = mac_address
self.udp_port = udp_port
# Platform ---------------------------------------------------------------------------------
if not args.sim:
self.platform = self.get_platform()
else:
self.platform = SimPlatform()
githash = git.Repo(
'.', search_parent_directories=True).git.rev_parse("HEAD")
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(
self,
self.platform,
sys_clk_freq,
ident="LiteX Row Hammer Tester SoC on {}, git: {}".format(
self.platform.device, githash),
ident_version=True,
integrated_rom_mode='rw' if args.rw_bios_mem else 'r',
**kwargs)
# CRG --------------------------------------------------------------------------------------
if not args.sim:
self.submodules.crg = self.get_crg()
else:
self.submodules.crg = CRG(self.platform.request('sys_clk'))
# Add dynamic simulation trace control, start enabled
self.platform.add_debug(self, reset=1)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads=self.platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
# SDRAM PHY --------------------------------------------------------------------------------
if sdram_module_spd_file is not None:
self.logger.info('Using DRAM module {} data: {}'.format(
colorer('SPD'), sdram_module_spd_file))
with open(sdram_module_spd_file, 'rb') as f:
spd_data = f.read()
module = SDRAMModule.from_spd_data(spd_data, self.sys_clk_freq)
else:
ratio = self.get_sdram_ratio()
self.logger.info('Using DRAM module {} ratio {}'.format(
colorer(sdram_module_cls.__name__), colorer(ratio)))
module = sdram_module_cls(self.sys_clk_freq,
ratio,
speedgrade=sdram_module_speedgrade)
if args.sim:
# Use the hardware platform to retrieve values for simulation
hw_pads = self.get_platform().request('ddram')
core_config = dict(
sdram_module_nb=len(hw_pads.dq) // 8, # number of byte groups
sdram_rank_nb=len(hw_pads.cs_n), # number of ranks
sdram_module=module,
memtype=module.memtype,
)
# Add IO pins
self.platform.add_extension(get_dram_ios(core_config))
phy_settings = get_sdram_phy_settings(
memtype=module.memtype,
data_width=core_config["sdram_module_nb"] * 8,
clk_freq=sys_clk_freq)
self.submodules.ddrphy = SDRAMPHYModel(
module=module,
settings=phy_settings,
clk_freq=sys_clk_freq,
verbosity=3,
)
else: # hardware
self.submodules.ddrphy = self.get_ddrphy()
self.add_csr("ddrphy")
# SDRAM Controller--------------------------------------------------------------------------
class ControllerDynamicSettings(Module, AutoCSR, AutoDoc, ModuleDoc):
"""Allows to change LiteDRAMController behaviour at runtime"""
def __init__(self):
self.refresh = CSRStorage(
reset=1,
description="Enable/disable Refresh commands sending")
self.submodules.controller_settings = ControllerDynamicSettings()
self.add_csr("controller_settings")
controller_settings = ControllerSettings()
controller_settings.with_auto_precharge = True
controller_settings.with_refresh = self.controller_settings.refresh.storage
controller_settings.refresh_cls = SyncableRefresher
assert self.ddrphy.settings.memtype == module.memtype, \
'Wrong DRAM module type: {} vs {}'.format(self.ddrphy.settings.memtype, module.memtype)
self.add_sdram("sdram",
phy=self.ddrphy,
module=module,
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=0,
controller_settings=controller_settings)
# CPU will report that leveling finished by writing to ddrctrl CSRs
self.submodules.ddrctrl = LiteDRAMCoreControl()
self.add_csr("ddrctrl")
# Ethernet / Etherbone ---------------------------------------------------------------------
if not args.sim:
self.add_host_bridge()
else: # simulation
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth"))
self.add_csr("ethphy")
# Ethernet Core
ethcore = LiteEthUDPIPCore(self.ethphy,
ip_address=self.ip_address,
mac_address=self.mac_address,
clk_freq=self.sys_clk_freq)
self.submodules.ethcore = ethcore
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp,
self.udp_port,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Rowhammer --------------------------------------------------------------------------------
self.submodules.rowhammer_dma = LiteDRAMDMAReader(
self.sdram.crossbar.get_port())
self.submodules.rowhammer = RowHammerDMA(self.rowhammer_dma)
self.add_csr("rowhammer")
# Bist -------------------------------------------------------------------------------------
if not args.no_memory_bist:
pattern_data_size = int(args.pattern_data_size, 0)
phy_settings = self.sdram.controller.settings.phy
pattern_data_width = phy_settings.dfi_databits * phy_settings.nphases
pattern_length = pattern_data_size // (pattern_data_width // 8)
assert pattern_data_size % (pattern_data_width//8) == 0, \
'Pattern data memory size must be multiple of {} bytes'.format(pattern_data_width//8)
self.submodules.pattern_mem = PatternMemory(
data_width=pattern_data_width, mem_depth=pattern_length)
self.add_memory(self.pattern_mem.data,
name='pattern_data',
origin=0x20000000)
self.add_memory(self.pattern_mem.addr,
name='pattern_addr',
origin=0x21000000)
self.logger.info(
'{}: Length: {}, Data Width: {}-bit, Address width: {}-bit'.
format(colorer('BIST pattern'), colorer(pattern_length),
colorer(pattern_data_width), colorer(32)))
assert controller_settings.address_mapping == 'ROW_BANK_COL'
row_offset = controller_settings.geom.bankbits + controller_settings.geom.colbits
inversion_kwargs = dict(
rowbits=int(self.args.bist_inversion_rowbits, 0),
row_shift=row_offset -
self.sdram.controller.interface.address_align,
)
# Writer
dram_wr_port = self.sdram.crossbar.get_port()
self.submodules.writer = Writer(dram_wr_port, self.pattern_mem,
**inversion_kwargs)
self.writer.add_csrs()
self.add_csr('writer')
# Reader
dram_rd_port = self.sdram.crossbar.get_port()
self.submodules.reader = Reader(dram_rd_port, self.pattern_mem,
**inversion_kwargs)
self.reader.add_csrs()
self.add_csr('reader')
assert pattern_data_width == dram_wr_port.data_width
assert pattern_data_width == dram_rd_port.data_width
# Payload executor -------------------------------------------------------------------------
if not args.no_payload_executor:
# TODO: disconnect bus during payload execution
phy_settings = self.sdram.controller.settings.phy
scratchpad_width = phy_settings.dfi_databits * phy_settings.nphases
payload_size = int(args.payload_size, 0)
scratchpad_size = int(args.scratchpad_size, 0)
assert payload_size % 4 == 0, 'Payload memory size must be multiple of 4 bytes'
assert scratchpad_size % (scratchpad_width//8) == 0, \
'Scratchpad memory size must be multiple of {} bytes'.format(scratchpad_width//8)
scratchpad_depth = scratchpad_size // (scratchpad_width // 8)
payload_mem = Memory(32, payload_size // 4)
scratchpad_mem = Memory(scratchpad_width, scratchpad_depth)
self.specials += payload_mem, scratchpad_mem
self.add_memory(payload_mem, name='payload', origin=0x30000000)
self.add_memory(scratchpad_mem,
name='scratchpad',
origin=0x31000000,
mode='r')
self.logger.info('{}: Length: {}, Data Width: {}-bit'.format(
colorer('Instruction payload'), colorer(payload_size // 4),
colorer(32)))
self.logger.info('{}: Length: {}, Data Width: {}-bit'.format(
colorer('Scratchpad memory'), colorer(scratchpad_depth),
colorer(scratchpad_width)))
self.submodules.dfi_switch = DFISwitch(
with_refresh=self.sdram.controller.settings.with_refresh,
dfii=self.sdram.dfii,
refresher_reset=self.sdram.controller.refresher.reset,
)
self.dfi_switch.add_csrs()
self.add_csr('dfi_switch')
self.submodules.payload_executor = PayloadExecutor(
mem_payload=payload_mem,
mem_scratchpad=scratchpad_mem,
dfi_switch=self.dfi_switch,
nranks=self.sdram.controller.settings.phy.nranks,
bankbits=self.sdram.controller.settings.geom.bankbits,
rowbits=self.sdram.controller.settings.geom.rowbits,
colbits=self.sdram.controller.settings.geom.colbits,
rdphase=self.sdram.controller.settings.phy.rdphase,
)
self.payload_executor.add_csrs()
self.add_csr('payload_executor')
def __init__(self,
board,
pnr_placer="heap",
pnr_seed=0,
usb_core="dummyusb",
usb_bridge=False,
**kwargs):
"""Create a basic SoC for Fomu.
Create a basic SoC for Fomu, including a 48 MHz and 12 MHz clock
domain called `usb_48` and `usb_12`. The `sys` frequency will
run at 12 MHz.
The USB core will optionally have a bridge to the Wishbone bus.
Args:
board (str): Which Fomu board to build for: pvt, evt, or hacker
pnr_placer (str): Which placer to use in nextpnr
pnr_seed (int): Which seed to use in nextpnr
usb_core (str): The name of the USB core to use, if any: dummyusb, epfifo
usb_bridge (bool): Whether to include a USB-to-Wishbone bridge
Raises:
ValueError: If either the `usb_core` or `board` are unrecognized
Returns:
Newly-constructed SoC
"""
if board == "pvt":
from litex_boards.partner.platforms.fomu_pvt import Platform
elif board == "hacker":
from litex_boards.partner.platforms.fomu_hacker import Platform
elif board == "evt":
from litex_boards.partner.platforms.fomu_evt import Platform
else:
raise ValueError("unrecognized fomu board: {}".format(board))
platform = Platform()
if "cpu_type" not in kwargs:
kwargs["cpu_type"] = None
kwargs["cpu_variant"] = None
clk_freq = int(12e6)
SoCCore.__init__(self,
platform,
clk_freq,
integrated_sram_size=0,
with_uart=False,
with_ctrl=False,
**kwargs)
self.submodules.crg = _CRG(platform)
# UP5K has single port RAM, which is a dedicated 128 kilobyte block.
# Use this as CPU RAM.
spram_size = 128 * 1024
self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus,
spram_size)
if usb_core is not None:
# Add USB pads. We use DummyUsb, which simply enumerates as a USB
# device. Then all interaction is done via the wishbone bridge.
usb_pads = platform.request("usb")
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n,
usb_pads.pullup)
if usb_core == "dummyusb":
self.submodules.usb = dummyusb.DummyUsb(usb_iobuf,
debug=usb_bridge)
elif usb_core == "epfifo":
self.submodules.usb = epfifo.PerEndpointFifo(usb_iobuf,
debug=usb_bridge)
else:
raise ValueError("unrecognized usb_core: {}".args(usb_core))
if usb_bridge:
self.add_wb_master(self.usb.debug_bridge.wishbone)
# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
# "-reult" adds an additional LUT pass to pack more stuff in, and
# "-dffe_min_ce_use 4" flag prevents Yosys from generating a
# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
# This increases density, and lets us use the FPGA more efficiently.
platform.toolchain.nextpnr_yosys_template[
2] += " -relut -dffe_min_ce_use 4"
# Allow us to set the nextpnr seed, because some values don't meet timing.
platform.toolchain.nextpnr_build_template[1] += " --seed " + str(
pnr_seed)
# Different placers can improve packing efficiency, however not all placers
# are enabled on all builds of nextpnr-ice40. Let the user override which
# placer they want to use.
if pnr_placer is not None:
platform.toolchain.nextpnr_build_template[
1] += " --placer {}".format(pnr_placer)
def __init__(self, platform, is_sim=False, debug=True, **kwargs):
clk_freq = int(12e6)
SoCCore.__init__(self,
platform,
clk_freq,
integrated_rom_size=16384,
integrated_sram_size=131072,
with_uart=True,
uart_stub=True,
**kwargs)
if is_sim:
self.submodules.crg = CocotbPlatform._CRG(self.platform)
else:
self.submodules.crg = _CRG(self.platform, fast_sysclk=False)
# Add a "Version" module so we can see what version of the board this is.
self.submodules.version = Version(
"proto2", [(0x02, "proto2", "Prototype Version 2 (red)")], 0)
# Add a "USB" module to let us debug the device.
usb_pads = platform.request("usb")
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
self.submodules.usb = ClockDomainsRenamer({
"usb_48": "clk48",
"usb_12": "clk12",
# })(DummyUsb(usb_iobuf, debug=debug, product="Hackaday Supercon Badge", cdc=True))
})(TriEndpointInterface(usb_iobuf, debug=debug))
dir_path = os.path.dirname(os.path.realpath(__file__))
if debug:
from litex.soc.cores.uart import UARTWishboneBridge
self.submodules.uart_bridge = UARTWishboneBridge(
platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
self.add_wb_master(self.usb.debug_bridge.wishbone)
if self.cpu_type is not None:
self.register_mem("vexriscv_debug", 0xf00f0000,
self.cpu.debug_bus, 0x200)
self.cpu.use_external_variant(dir_path +
"/rtl/VexRiscv_HaD_Debug.v")
elif self.cpu_type is not None:
self.cpu.use_external_variant(dir_path + "/rtl/VexRiscv_HaD.v")
# Add the 16 MB SPI flash as XIP memory at address 0x03000000
if not is_sim:
flash = SpiFlashDualQuad(platform.request("spiflash4x"),
dummy=6,
endianness="little")
flash.add_clk_primitive(self.platform.device)
self.submodules.lxspi = flash
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.lxspi.bus,
size=16 * 1024 * 1024)
# self.submodules.picorvspi = flash = PicoRVSpi(self.platform, pads=platform.request("spiflash"), size=16 * 1024 * 1024)
# self.register_mem("spiflash", self.mem_map["spiflash"], self.picorvspi.bus, size=self.picorvspi.size)
self.add_constant("ROM_BOOT_ADDRESS",
self.mem_map["spiflash"] + 0x300000)
# # Add the 16 MB SPI RAM at address 0x40000000 # Value at 40010000: afbfcfef
reset_cycles = 2**14 - 1
if is_sim:
reset_cycles = 0
ram = SpiRamDualQuad(platform.request("spiram4x", 0),
platform.request("spiram4x", 1),
dummy=5,
reset_cycles=reset_cycles,
qpi=True)
self.submodules.ram = ram
self.register_mem("main_ram",
self.mem_map["main_ram"],
self.ram.bus,
size=16 * 1024 * 1024)
# Let us reboot the device
self.submodules.reboot = Reboot(platform.request("programn"))
# Add a Messible for sending messages to the host
self.submodules.messible = Messible()
# Add an LCD so we can see what's up
self.submodules.lcdif = LCDIF(platform.request("lcd"))
# Ensure timing is correctly set up
if not is_sim:
self.platform.toolchain.build_template[
1] += " --speed 8" # Add "speed grade 8" to nextpnr-ecp5
self.platform.toolchain.freq_constraints["sys"] = 48
if is_sim:
self.add_wb_master(self.platform.request("wishbone"))
# SAO
if not kwargs["sao0_disable"]:
self.submodules.sao0 = ShittyAddOn(
self.platform,
self.platform.request("sao", 0),
disable_i2c=kwargs["sao0_disable_i2c"])
self.add_csr("sao0")
if not kwargs["sao1_disable"]:
self.submodules.sao1 = ShittyAddOn(
self.platform,
self.platform.request("sao", 1),
disable_i2c=kwargs["sao1_disable_i2c"])
self.add_csr("sao1")
# PMOD
platform.add_extension(_pmod_gpio)
self.submodules.pmod = GPIOBidirectional(
self.platform.request("pmod_gpio"))
self.add_csr("pmod")
# GENIO
if not kwargs["genio_disable"]:
platform.add_extension(_genio_gpio)
self.submodules.genio = GPIOBidirectional(
self.platform.request("genio_gpio"))
self.add_csr("genio")
# LEDs
self.submodules.led0 = gpio.GPIOOut(self.platform.request("led", 0))
self.add_csr("led0")
self.submodules.led1 = gpio.GPIOOut(self.platform.request("led", 1))
self.add_csr("led1")
# Keypad
self.submodules.keypad = gpio.GPIOIn(
Cat(self.platform.request("keypad", 0).flatten()))
self.add_csr("keypad")
def __init__(self,
pnr_placer="heap",
pnr_seed=0,
debug=True,
boot_vector=0x20020000,
**kwargs):
"""Create a basic SoC for iCEBreaker.
Create a basic SoC for iCEBreaker. The `sys` frequency will run at 12 MHz.
Args:
pnr_placer (str): Which placer to use in nextpnr
pnr_seed (int): Which seed to use in nextpnr
Returns:
Newly-constructed SoC
"""
platform = Platform()
if "cpu_type" not in kwargs:
kwargs["cpu_type"] = None
kwargs["cpu_variant"] = None
else:
kwargs["cpu_reset_address"] = boot_vector
clk_freq = int(12e6)
# Force the SRAM size to 0, because we add our own SRAM with SPRAM
kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0
if debug:
kwargs["uart_name"] = "crossover"
if kwargs["cpu_type"] == "vexriscv":
kwargs["cpu_variant"] = kwargs["cpu_variant"] + "+debug"
SoCCore.__init__(self,
platform,
clk_freq,
with_uart=True,
with_ctrl=True,
**kwargs)
# If there is a VexRiscv CPU, add a fake ROM that simply tells the CPU
# to jump to the given address.
if hasattr(self, "cpu") and self.cpu.name == "vexriscv":
self.add_memory_region("rom", 0, 16)
self.submodules.rom = JumpToAddressROM(16, boot_vector)
self.submodules.crg = _CRG(platform)
# UP5K has single port RAM, which is a dedicated 128 kilobyte block.
# Use this as CPU RAM.
spram_size = 128 * 1024
self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus,
spram_size)
# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
# for doing writes.
spi_pads = platform.request("spiflash4x")
self.submodules.lxspi = spi_flash.SpiFlash(spi_pads,
dummy=6,
endianness="little")
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.lxspi.bus,
size=16 * 1024 * 1024)
self.add_csr("lxspi")
# In debug mode, add a UART bridge. This takes over from the normal UART bridge,
# however you can use the "crossover" UART to communicate with this over the bridge.
if debug:
self.submodules.uart_bridge = UARTWishboneBridge(
platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
if hasattr(self, "cpu") and self.cpu.name == "vexriscv":
self.register_mem("vexriscv_debug", 0xf00f0000,
self.cpu.debug_bus, 0x100)
ledsignals = Signal(2)
self.submodules.leds = GPIOOut(ledsignals)
self.comb += platform.request("user_ledr_n").eq(ledsignals[0])
self.comb += platform.request("user_ledg_n").eq(ledsignals[1])
self.add_csr("leds")
# Override default LiteX's yosys/build templates
assert hasattr(platform.toolchain, "yosys_template")
assert hasattr(platform.toolchain, "build_template")
platform.toolchain.yosys_template = [
"{read_files}",
"attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
"synth_ice40 -json {build_name}.json -top {build_name}",
]
platform.toolchain.build_template = [
"yosys -q -l {build_name}.rpt {build_name}.ys",
"nextpnr-ice40 --json {build_name}.json --pcf {build_name}.pcf --asc {build_name}.txt \
--pre-pack {build_name}_pre_pack.py --{architecture} --package {package}",
"icepack {build_name}.txt {build_name}.bin"
]
# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
# The "-reult" adds an additional LUT pass to pack more stuff in,
# and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
# This increases density, and lets us use the FPGA more efficiently.
platform.toolchain.yosys_template[
2] += " -relut -abc2 -dffe_min_ce_use 4 -relut"
# if use_dsp:
# platform.toolchain.yosys_template[2] += " -dsp"
# Disable final deep-sleep power down so firmware words are loaded
# onto softcore's address bus.
platform.toolchain.build_template[
2] = "icepack -s {build_name}.txt {build_name}.bin"
# Allow us to set the nextpnr seed
platform.toolchain.build_template[1] += " --seed " + str(pnr_seed)
if pnr_placer is not None:
platform.toolchain.build_template[1] += " --placer {}".format(
pnr_placer)
def __init__(self, flash_offset, sys_clk_freq, **kwargs):
"""Create a basic SoC for iCEBreaker.
Returns:
Newly-constructed SoC
"""
platform = Platform()
# Use SERV CPU buy default
if "cpu_type" not in kwargs:
kwargs["cpu_type"] = "serv"
kwargs["cpu_variant"] = "standard"
else:
if kwargs["cpu_type"] == "vexriscv" and ("cpu_variant"
not in kwargs):
kwargs["cpu_variant"] = "minimal"
# Force the SRAM size to 0, because we add our own SRAM with SPRAM
kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0
# Set CPU reset address
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + flash_offset
# SoCCore
SoCCore.__init__(self, platform, sys_clk_freq, **kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# UP5K has single port RAM, which is a dedicated 128 kilobyte block.
# Use this as CPU RAM.
spram_size = 128 * 1024
self.submodules.spram = Up5kSPRAM(size=spram_size)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus,
spram_size)
# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
# for doing writes.
spiflash_size = 16 * 1024 * 1024
self.submodules.spiflash = SpiFlash(platform.request("spiflash4x"),
dummy=6,
endianness="little")
self.add_csr("spiflash")
# SPI flash cache
l2_cache_size = 8192
if l2_cache_size != 0:
self.submodules.l2_cache = wishbone.Cache(
cachesize=l2_cache_size // 4,
master=wishbone.Interface(32),
slave=self.spiflash.bus,
)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.l2_cache.master,
size=spiflash_size)
else:
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=spiflash_size)
# Add ROM linker region
self.add_memory_region("rom",
self.mem_map["spiflash"] + flash_offset,
spiflash_size - flash_offset,
type="cached+linker")
# User button as reset
reset_btn = platform.request("user_btn_n")
self.comb += self.crg.reset.eq(~reset_btn)
# Clock peripheral holds the actual sys_clk frequency
self.submodules.clock = ClockPeripheral(sys_clk_freq)
self.add_csr("clock")
# GPIO peripheral
pin_names = ["PMOD1A:%d" % i for i in range(8)] +\
["PMOD1B:%d" % i for i in range(8)] +\
["PMOD2:%d" % i for i in range(8)]
gpio_extension = [("gpio", i, Pins(name), IOStandard("LVCMOS33"))
for i, name in enumerate(pin_names)]
platform.add_extension(gpio_extension)
gpio = []
for i in range(len(pin_names)):
gpio.append(platform.request("gpio"))
self.submodules.gpio = GPIOPeripheral(gpio + [
platform.request("user_ledr_n"),
platform.request("user_ledg_n"),
])
self.add_csr("gpio")
# Suppress synthesis output
assert hasattr(self.platform.toolchain, "build_template")
if self.platform.toolchain.build_template[0].startswith("yosys "):
self.platform.toolchain.build_template[0] = \
self.platform.toolchain.build_template[0].replace("yosys ", "yosys -q ")
def __init__(self, platform, output_dir="build", **kwargs):
# Disable integrated RAM as we'll add it later
self.integrated_sram_size = 0
self.output_dir = output_dir
clk_freq = int(12e6)
self.submodules.crg = _CRG(platform)
SoCCore.__init__(self, platform, clk_freq,
cpu_type=None,
integrated_rom_size=0x0,
integrated_sram_size=0x0,
integrated_main_ram_size=0x0,
csr_address_width=14, csr_data_width=8,
with_uart=False, with_timer=False)
# USB signals
usb_p_tx = Signal()
usb_n_tx = Signal()
usb_p_rx = Signal()
usb_n_rx = Signal()
usb_tx_en = Signal()
usb_p_t = TSTriple()
usb_n_t = TSTriple()
usb_pads = platform.request("usb")
# Assign signals to triple
self.comb += [
If(usb_tx_en,
usb_p_rx.eq(0b1),
usb_n_rx.eq(0b0),
).Else(
usb_p_rx.eq(usb_p_t.i),
usb_n_rx.eq(usb_n_t.i),
),
usb_p_t.oe.eq(usb_tx_en),
usb_n_t.oe.eq(usb_tx_en),
usb_p_t.o.eq(usb_p_tx),
usb_n_t.o.eq(usb_n_tx),
]
# Assign pads to triple
self.specials += usb_p_t.get_tristate(usb_pads.d_p)
self.specials += usb_n_t.get_tristate(usb_pads.d_n)
self.comb += usb_pads.tx_en.eq(usb_tx_en)
self.comb += usb_pads.pullup.eq(0b1)
platform.add_source("../tinyfpga/common/tinyfpga_bootloader.v")
self.specials += Instance("tinyfpga_bootloader",
i_clk_48mhz=self.crg.cd_usb_48.clk,
i_clk=self.crg.cd_usb_48.clk,
i_reset=self.crg.cd_sys.rst,
# USB lines
o_usb_p_tx=usb_p_tx,
o_usb_n_tx=usb_n_tx,
i_usb_p_rx=usb_p_rx,
i_usb_n_rx=usb_n_rx,
o_usb_tx_en=usb_tx_en
)
def __init__(self, platform, revision="sata_gen3", trx_dw=16, nphys=4):
self.nphys = nphys
clk_freq = 200 * 1000000
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="LiteSATA example design",
with_timer=False)
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform)
# SATA PHYs
self.sata_phys = []
for i in range(self.nphys):
sata_phy = LiteSATAPHY(
platform.device,
platform.request("sata_clocks")
if i == 0 else self.sata_phys[0].crg.refclk,
platform.request("sata", i), revision, clk_freq, trx_dw)
sata_phy = ClockDomainsRenamer({
"sata_rx":
"sata_rx{}".format(str(i)),
"sata_tx":
"sata_tx{}".format(str(i))
})(sata_phy)
setattr(self.submodules, "sata_phy{}".format(str(i)), sata_phy)
self.sata_phys.append(sata_phy)
# SATA Cores
self.sata_cores = []
for i in range(self.nphys):
sata_core = LiteSATACore(self.sata_phys[i])
setattr(self.submodules, "sata_core{}".format(str(i)), sata_core)
self.sata_cores.append(sata_core)
# SATA Frontend
self.submodules.sata_mirroring = LiteSATAMirroring(self.sata_cores)
self.sata_crossbars = []
for i in range(self.nphys):
sata_crossbar = LiteSATACrossbar(self.sata_mirroring.ports[i])
setattr(self.submodules, "sata_crossbar{}".format(str(i)),
sata_crossbar)
self.sata_crossbars.append(sata_crossbar)
# SATA Application
self.sata_bists = []
for i in range(self.nphys):
sata_bist = LiteSATABIST(self.sata_crossbars[i], with_csr=True)
setattr(self.submodules, "sata_bist{}".format(str(i)), sata_bist)
self.sata_bists.append(sata_bist)
# Status Leds
self.submodules.status_leds = StatusLeds(platform, self.sata_phys)
platform.add_platform_command("""
create_clock -name sys_clk -period 5 [get_nets sys_clk]
""")
for i in range(len(self.sata_phys)):
self.specials += [
Keep(ClockSignal("sata_rx{}".format(str(i)))),
Keep(ClockSignal("sata_tx{}".format(str(i))))
]
platform.add_platform_command("""
create_clock -name {sata_rx_clk} -period {sata_clk_period} [get_nets {sata_rx_clk}]
create_clock -name {sata_tx_clk} -period {sata_clk_period} [get_nets {sata_tx_clk}]
set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_rx_clk}]
set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_tx_clk}]
set_false_path -from [get_clocks {sata_rx_clk}] -to [get_clocks sys_clk]
set_false_path -from [get_clocks {sata_tx_clk}] -to [get_clocks sys_clk]
""".format(sata_rx_clk="sata_rx{}_clk".format(str(i)),
sata_tx_clk="sata_tx{}_clk".format(str(i)),
sata_clk_period="3.3" if trx_dw == 16 else "6.6"))
def __init__(self, platform, boot_source="rand",
debug=None, bios_file=None,
use_dsp=False, placer="heap", output_dir="build",
pnr_seed=0,
warmboot_offsets=None,
**kwargs):
# Disable integrated RAM as we'll add it later
self.integrated_sram_size = 0
self.output_dir = output_dir
clk_freq = int(12e6)
self.submodules.crg = _CRG(platform)
SoCCore.__init__(self, platform, clk_freq, integrated_sram_size=0, with_uart=False, **kwargs)
usb_debug = False
if debug is not None:
if debug == "uart":
from litex.soc.cores.uart import UARTWishboneBridge
self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
elif debug == "usb":
usb_debug = True
elif debug == "spi":
import spibone
# Add SPI Wishbone bridge
debug_device = [
("spidebug", 0,
Subsignal("mosi", Pins("dbg:0")),
Subsignal("miso", Pins("dbg:1")),
Subsignal("clk", Pins("dbg:2")),
Subsignal("cs_n", Pins("dbg:3")),
)
]
platform.add_extension(debug_device)
spi_pads = platform.request("spidebug")
self.submodules.spibone = ClockDomainsRenamer("usb_12")(spibone.SpiWishboneBridge(spi_pads, wires=4))
self.add_wb_master(self.spibone.wishbone)
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
self.cpu.use_external_variant("rtl/VexRiscv_Fomu_Debug.v")
os.path.join(output_dir, "gateware")
self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x100)
else:
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
self.cpu.use_external_variant("rtl/VexRiscv_Fomu.v")
# SPRAM- UP5K has single port RAM, might as well use it as SRAM to
# free up scarce block RAM.
spram_size = 128*1024
self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus, spram_size)
# Add a Messible for device->host communications
self.submodules.messible = Messible()
if boot_source == "rand":
kwargs['cpu_reset_address'] = 0
bios_size = 0x2000
self.submodules.random_rom = RandomFirmwareROM(bios_size)
self.add_constant("ROM_DISABLE", 1)
self.register_rom(self.random_rom.bus, bios_size)
elif boot_source == "bios":
kwargs['cpu_reset_address'] = 0
if bios_file is None:
self.integrated_rom_size = bios_size = 0x2000
self.submodules.rom = wishbone.SRAM(bios_size, read_only=True, init=[])
self.register_rom(self.rom.bus, bios_size)
else:
bios_size = 0x2000
self.submodules.firmware_rom = FirmwareROM(bios_size, bios_file)
self.add_constant("ROM_DISABLE", 1)
self.register_rom(self.firmware_rom.bus, bios_size)
elif boot_source == "spi":
kwargs['cpu_reset_address'] = 0
self.integrated_rom_size = bios_size = 0x2000
gateware_size = 0x1a000
self.flash_boot_address = self.mem_map["spiflash"] + gateware_size
self.submodules.rom = wishbone.SRAM(bios_size, read_only=True, init=[])
self.register_rom(self.rom.bus, bios_size)
else:
raise ValueError("unrecognized boot_source: {}".format(boot_source))
# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
# for doing writes.
spi_pads = platform.request("spiflash4x")
self.submodules.lxspi = spi_flash.SpiFlashDualQuad(spi_pads, dummy=platform.spi_dummy, endianness="little")
self.register_mem("spiflash", self.mem_map["spiflash"], self.lxspi.bus, size=platform.spi_size)
# Add USB pads, as well as the appropriate USB controller. If no CPU is
# present, use the DummyUsb controller.
usb_pads = platform.request("usb")
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
self.submodules.usb = eptri.TriEndpointInterface(usb_iobuf, debug=usb_debug)
else:
self.submodules.usb = dummyusb.DummyUsb(usb_iobuf, debug=usb_debug)
if usb_debug:
self.add_wb_master(self.usb.debug_bridge.wishbone)
# For the EVT board, ensure the pulldown pin is tristated as an input
if hasattr(usb_pads, "pulldown"):
pulldown = TSTriple()
self.specials += pulldown.get_tristate(usb_pads.pulldown)
self.comb += pulldown.oe.eq(0)
# Add GPIO pads for the touch buttons
platform.add_extension(TouchPads.touch_device)
self.submodules.touch = TouchPads(platform.request("touch_pads"))
# Allow the user to reboot the ICE40. Additionally, connect the CPU
# RESET line to a register that can be modified, to allow for
# us to debug programs even during reset.
self.submodules.reboot = SBWarmBoot(self, warmboot_offsets)
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
self.cpu.cpu_params.update(
i_externalResetVector=self.reboot.addr.storage,
)
self.submodules.rgb = SBLED(platform.revision, platform.request("rgb_led"))
self.submodules.version = Version(platform.revision, self, pnr_seed, models=[
("0x45", "E", "Fomu EVT"),
("0x44", "D", "Fomu DVT"),
("0x50", "P", "Fomu PVT (production)"),
("0x48", "H", "Fomu Hacker"),
("0x3f", "?", "Unknown model"),
])
# Override default LiteX's yosys/build templates
assert hasattr(platform.toolchain, "yosys_template")
assert hasattr(platform.toolchain, "build_template")
platform.toolchain.yosys_template = [
"{read_files}",
"attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
"synth_ice40 -json {build_name}.json -top {build_name}",
]
platform.toolchain.build_template = [
"yosys -q -l {build_name}.rpt {build_name}.ys",
"nextpnr-ice40 --json {build_name}.json --pcf {build_name}.pcf --asc {build_name}.txt \
--pre-pack {build_name}_pre_pack.py --{architecture} --package {package}",
"icepack {build_name}.txt {build_name}.bin"
]
# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
# The "-reult" adds an additional LUT pass to pack more stuff in,
# and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
# This increases density, and lets us use the FPGA more efficiently.
platform.toolchain.yosys_template[2] += " -relut -abc2 -dffe_min_ce_use 4 -relut"
if use_dsp:
platform.toolchain.yosys_template[2] += " -dsp"
# Disable final deep-sleep power down so firmware words are loaded
# onto softcore's address bus.
platform.toolchain.build_template[2] = "icepack -s {build_name}.txt {build_name}.bin"
# Allow us to set the nextpnr seed
platform.toolchain.build_template[1] += " --seed " + str(pnr_seed)
if placer is not None:
platform.toolchain.build_template[1] += " --placer {}".format(placer)
def __init__(self, platform, revision="sata_gen3", trx_dw=16, nphys=4):
self.nphys = nphys
clk_freq = 200*1000000
SoCCore.__init__(self, platform, clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="LiteSATA example design",
with_timer=False)
self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.submodules.crg = CRG(platform)
# SATA PHYs
self.sata_phys = []
for i in range(self.nphys):
sata_phy = LiteSATAPHY(platform.device,
platform.request("sata_clocks") if i == 0 else self.sata_phys[0].crg.refclk,
platform.request("sata", i),
revision,
clk_freq,
trx_dw)
sata_phy = ClockDomainsRenamer({"sata_rx": "sata_rx{}".format(str(i)),
"sata_tx": "sata_tx{}".format(str(i))})(sata_phy)
setattr(self.submodules, "sata_phy{}".format(str(i)), sata_phy)
self.sata_phys.append(sata_phy)
# SATA Cores
self.sata_cores = []
for i in range(self.nphys):
sata_core = LiteSATACore(self.sata_phys[i])
setattr(self.submodules, "sata_core{}".format(str(i)), sata_core)
self.sata_cores.append(sata_core)
# SATA Frontend
self.submodules.sata_mirroring = LiteSATAMirroring(self.sata_cores)
self.sata_crossbars = []
for i in range(self.nphys):
sata_crossbar = LiteSATACrossbar(self.sata_mirroring.ports[i])
setattr(self.submodules, "sata_crossbar{}".format(str(i)), sata_crossbar)
self.sata_crossbars.append(sata_crossbar)
# SATA Application
self.sata_bists = []
for i in range(self.nphys):
sata_bist = LiteSATABIST(self.sata_crossbars[i], with_csr=True)
setattr(self.submodules, "sata_bist{}".format(str(i)), sata_bist)
self.sata_bists.append(sata_bist)
# Status Leds
self.submodules.status_leds = StatusLeds(platform, self.sata_phys)
platform.add_platform_command("""
create_clock -name sys_clk -period 5 [get_nets sys_clk]
""")
for i in range(len(self.sata_phys)):
self.specials += [
Keep(ClockSignal("sata_rx{}".format(str(i)))),
Keep(ClockSignal("sata_tx{}".format(str(i))))
]
platform.add_platform_command("""
create_clock -name {sata_rx_clk} -period {sata_clk_period} [get_nets {sata_rx_clk}]
create_clock -name {sata_tx_clk} -period {sata_clk_period} [get_nets {sata_tx_clk}]
set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_rx_clk}]
set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_tx_clk}]
set_false_path -from [get_clocks {sata_rx_clk}] -to [get_clocks sys_clk]
set_false_path -from [get_clocks {sata_tx_clk}] -to [get_clocks sys_clk]
""".format(sata_rx_clk="sata_rx{}_clk".format(str(i)),
sata_tx_clk="sata_tx{}_clk".format(str(i)),
sata_clk_period="3.3" if trx_dw == 16 else "6.6"))
