def test_multiple_interface(self): # the following calls used to create issues (several interfaces from # the same device) ftdi1 = Ftdi() ftdi1.open(interface=1) ftdi2 = Ftdi() ftdi2.open(interface=2) import time for x in range(5): print "If#1: ", hex(ftdi1.poll_modem_status()) print "If#2: ", ftdi2.modem_status() time.sleep(0.500) ftdi1.close() ftdi2.close()
class JtagController(object): """JTAG master of an FTDI device""" TCK_BIT = 0x01 # FTDI output TDI_BIT = 0x02 # FTDI output TDO_BIT = 0x04 # FTDI input TMS_BIT = 0x08 # FTDI output TRST_BIT = 0x10 # FTDI output, not available on 2232 JTAG debugger JTAG_MASK = 0x1f FTDI_PIPE_LEN = 512 # Private API def __init__(self, trst=False, frequency=3.0E6): """ trst uses the nTRST optional JTAG line to hard-reset the TAP controller """ self._ftdi = Ftdi() self._trst = trst self._frequency = frequency self.direction = JtagController.TCK_BIT | \ JtagController.TDI_BIT | \ JtagController.TMS_BIT | \ (self._trst and JtagController.TRST_BIT or 0) self._last = None # Last deferred TDO bit self._write_buff = Array('B') def __del__(self): self.close() # Public API def configure(self, vendor, product, interface): """Configure the FTDI interface as a JTAG controller""" curfreq = self._ftdi.open_mpsse(vendor, product, interface, direction=self.direction, #initial=0x0, frequency=self._frequency) # FTDI requires to initialize all GPIOs before MPSSE kicks in cmd = Array('B', [Ftdi.SET_BITS_LOW, 0x0, self.direction]) self._ftdi.write_data(cmd) def close(self): if self._ftdi: self._ftdi.close() self._ftdi = None def purge(self): self._ftdi.purge_buffers() def reset(self, sync=False): """Reset the attached TAP controller. sync sends the command immediately (no caching) """ # we can either send a TRST HW signal or perform 5 cycles with TMS=1 # to move the remote TAP controller back to 'test_logic_reset' state # do both for now if not self._ftdi: raise JtagError("FTDI controller terminated") if self._trst: # nTRST value = 0 cmd = Array('B', [Ftdi.SET_BITS_LOW, value, self.direction]) self._ftdi.write_data(cmd) time.sleep(0.1) # nTRST should be left to the high state value = JtagController.TRST_BIT cmd = Array('B', [Ftdi.SET_BITS_LOW, value, self.direction]) self._ftdi.write_data(cmd) time.sleep(0.1) # TAP reset (even with HW reset, could be removed though) self.write_tms(BitSequence('11111')) if sync: self.sync() def sync(self): if not self._ftdi: raise JtagError("FTDI controller terminated") if self._write_buff: self._ftdi.write_data(self._write_buff) self._write_buff = Array('B') def write_tms(self, tms): """Change the TAP controller state""" if not isinstance(tms, BitSequence): raise JtagError('Expect a BitSequence') length = len(tms) if not (0 < length < 8): raise JtagError('Invalid TMS length') out = BitSequence(tms, length=8) # apply the last TDO bit if self._last is not None: out[7] = self._last # print "TMS", tms, (self._last is not None) and 'w/ Last' or '' # reset last bit self._last = None cmd = Array('B', [Ftdi.WRITE_BITS_TMS_NVE, length-1, out.tobyte()]) self._stack_cmd(cmd) self.sync() #self._ftdi.validate_mpsse() def read(self, length): """Read out a sequence of bits from TDO""" byte_count = length//8 bit_count = length-8*byte_count bs = BitSequence() if byte_count: bytes = self._read_bytes(byte_count) bs.append(bytes) if bit_count: bits = self._read_bits(bit_count) bs.append(bits) return bs def write(self, out, use_last=True): """Write a sequence of bits to TDI""" if isinstance(out, str): out = BitSequence(bytes_=out) elif not isinstance(out, BitSequence): out = BitSequence(out) if use_last: (out, self._last) = (out[:-1], bool(out[-1])) byte_count = len(out)//8 pos = 8*byte_count bit_count = len(out)-pos if byte_count: self._write_bytes(out[:pos]) if bit_count: self._write_bits(out[pos:]) def shift_register(self, out, use_last=False): """Shift a BitSequence into the current register and retrieve the register output""" if not isinstance(out, BitSequence): return JtagError('Expect a BitSequence') length = len(out) if use_last: (out, self._last) = (out[:-1], int(out[-1])) byte_count = len(out)//8 pos = 8*byte_count bit_count = len(out)-pos if not byte_count and not bit_count: raise JtagError("Nothing to shift") if byte_count: blen = byte_count-1 #print "RW OUT %s" % out[:pos] cmd = Array('B', [Ftdi.RW_BYTES_PVE_NVE_LSB, blen, (blen>>8)&0xff]) cmd.extend(out[:pos].tobytes(msby=True)) self._stack_cmd(cmd) #print "push %d bytes" % byte_count if bit_count: #print "RW OUT %s" % out[pos:] cmd = Array('B', [Ftdi.RW_BITS_PVE_NVE_LSB, bit_count-1]) cmd.append(out[pos:].tobyte()) self._stack_cmd(cmd) #print "push %d bits" % bit_count self.sync() bs = BitSequence() byte_count = length//8 pos = 8*byte_count bit_count = length-pos if byte_count: data = self._ftdi.read_data_bytes(byte_count, 4) if not data: raise JtagError('Unable to read data from FTDI') byteseq = BitSequence(bytes_=data, length=8*byte_count) #print "RW IN %s" % byteseq bs.append(byteseq) #print "pop %d bytes" % byte_count if bit_count: data = self._ftdi.read_data_bytes(1, 4) if not data: raise JtagError('Unable to read data from FTDI') byte = data[0] # need to shift bits as they are shifted in from the MSB in FTDI byte >>= 8-bit_count bitseq = BitSequence(byte, length=bit_count) bs.append(bitseq) #print "pop %d bits" % bit_count if len(bs) != length: raise AssertionError("Internal error") #self._ftdi.validate_mpsse() return bs def _stack_cmd(self, cmd): if not isinstance(cmd, Array): raise TypeError('Expect a byte array') if not self._ftdi: raise JtagError("FTDI controller terminated") # Currrent buffer + new command + send_immediate if (len(self._write_buff)+len(cmd)+1) >= JtagController.FTDI_PIPE_LEN: self.sync() self._write_buff.extend(cmd) def _read_bits(self, length): """Read out bits from TDO""" data = '' if length > 8: raise JtagError("Cannot fit into FTDI fifo") cmd = Array('B', [Ftdi.READ_BITS_NVE_LSB, length-1]) self._stack_cmd(cmd) self.sync() data = self._ftdi.read_data_bytes(1, 4) # need to shift bits as they are shifted in from the MSB in FTDI byte = ord(data) >> 8-bit_count bs = BitSequence(byte, length=length) #print "READ BITS %s" % (bs) return bs def _write_bits(self, out): """Output bits on TDI""" length = len(out) byte = out.tobyte() #print "WRITE BITS %s" % out cmd = Array('B', [Ftdi.WRITE_BITS_NVE_LSB, length-1, byte]) self._stack_cmd(cmd) def _read_bytes(self, length): """Read out bytes from TDO""" data = '' if length > JtagController.FTDI_PIPE_LEN: raise JtagError("Cannot fit into FTDI fifo") alen = length-1 cmd = Array('B', [Ftdi.READ_BYTES_NVE_LSB, alen&0xff, (alen>>8)&0xff]) self._stack_cmd(cmd) self.sync() data = self._ftdi.read_data_bytes(length, 4) bs = BitSequence(bytes_=data, length=8*length) #print "READ BYTES %s" % bs return bs def _write_bytes(self, out): """Output bytes on TDI""" bytes_ = out.tobytes(msby=True) # don't ask... olen = len(bytes_)-1 #print "WRITE BYTES %s" % out cmd = Array('B', [Ftdi.WRITE_BYTES_NVE_LSB, olen&0xff, (olen>>8)&0xff]) cmd.extend(bytes_) self._stack_cmd(cmd)
class SpiController(object): """SPI master""" SCK_BIT = 0x01 DO_BIT = 0x02 DI_BIT = 0x04 CS_BIT = 0x08 PAYLOAD_MAX_LENGTH = 0x10000 # 16 bits max def __init__(self, silent_clock=False, cs_count=4): """Instanciate a SpiController. silent_clock should be set to avoid clocking out SCLK when all /CS signals are released. This clock beat is used to enforce a delay between /CS signal activation. When weird SPI devices are used, SCLK beating may cause trouble. In this case, silent_clock should be set but beware that SCLK line should be fitted with a pull-down resistor, as SCLK is high-Z during this short period of time. cs_count is the number of /CS lines (one per device to drive on the SPI bus) """ self._ftdi = Ftdi() self._cs_bits = ((SpiController.CS_BIT << cs_count) - 1) & \ ~(SpiController.CS_BIT - 1) self._ports = [None] * cs_count self._direction = self._cs_bits | \ SpiController.DO_BIT | \ SpiController.SCK_BIT self._cs_high = Array('B') if silent_clock: # Set SCLK as input to avoid emitting clock beats self._cs_high.extend([Ftdi.SET_BITS_LOW, self._cs_bits, self._direction&~SpiController.SCK_BIT]) # /CS to SCLK delay, use 8 clock cycles as a HW tempo self._cs_high.extend([Ftdi.WRITE_BITS_TMS_NVE, 8-1, 0xff]) # Restore idle state self._cs_high.extend([Ftdi.SET_BITS_LOW, self._cs_bits, self._direction]) self._immediate = Array('B', [Ftdi.SEND_IMMEDIATE]) self._frequency = 0.0 def configure(self, vendor, product, interface, frequency=6.0E6, loopback=False): """Configure the FTDI interface as a SPI master""" self._frequency = \ self._ftdi.open_mpsse(vendor, product, interface, direction=self._direction, initial=self._cs_bits, # /CS all high frequency=frequency, loopback=loopback) def terminate(self): """Close the FTDI interface""" if self._ftdi: self._ftdi.close() self._ftdi = None def get_port(self, cs): """Obtain a SPI port to drive a SPI device selected by cs""" if not self._ftdi: raise SpiIOError("FTDI controller not initialized") if cs >= len(self._ports): raise SpiIOError("No such SPI port") if not self._ports[cs]: cs_state = 0xFF & ~((SpiController.CS_BIT<<cs) | SpiController.SCK_BIT | SpiController.DO_BIT) cs_cmd = Array('B', [Ftdi.SET_BITS_LOW, cs_state, self._direction]) self._ports[cs] = SpiPort(self, cs_cmd) self._flush() return self._ports[cs] @property def frequency_max(self): """Returns the maximum SPI clock""" return self._ftdi.frequency_max @property def frequency(self): """Returns the current SPI clock""" return self._frequency def _exchange(self, frequency, cs_cmd, out, readlen): """Perform a half-duplex transaction with the SPI slave""" if not self._ftdi: raise SpiIOError("FTDI controller not initialized") if len(out) > SpiController.PAYLOAD_MAX_LENGTH: raise SpiIOError("Output payload is too large") if readlen > SpiController.PAYLOAD_MAX_LENGTH: raise SpiIOError("Input payload is too large") if self._frequency != frequency: freq = self._ftdi.set_frequency(frequency) # store the requested value, not the actual one (best effort) self._frequency = frequency write_cmd = struct.pack('<BH', Ftdi.WRITE_BYTES_NVE_MSB, len(out)-1) if readlen: read_cmd = struct.pack('<BH', Ftdi.READ_BYTES_NVE_MSB, readlen-1) cmd = Array('B', cs_cmd) cmd.fromstring(write_cmd) cmd.extend(out) cmd.fromstring(read_cmd) cmd.extend(self._immediate) cmd.extend(self._cs_high) self._ftdi.write_data(cmd) # USB read cycle may occur before the FTDI device has actually # sent the data, so try to read more than once if no data is # actually received data = self._ftdi.read_data_bytes(readlen, 4) else: cmd = Array('B', cs_cmd) cmd.fromstring(write_cmd) cmd.extend(out) cmd.extend(self._cs_high) self._ftdi.write_data(cmd) data = Array('B') return data def _flush(self): """Flush the HW FIFOs""" self._ftdi.write_data(self._immediate) self._ftdi.purge_buffers()
class JtagController(object): """JTAG master of an FTDI device""" TCK_BIT = 0x01 # FTDI output TDI_BIT = 0x02 # FTDI output TDO_BIT = 0x04 # FTDI input TMS_BIT = 0x08 # FTDI output TRST_BIT = 0x10 # FTDI output, not available on 2232 JTAG debugger JTAG_MASK = 0x1f FTDI_PIPE_LEN = 512 # Private API def __init__(self, trst=False, frequency=3.0E6): """ trst uses the nTRST optional JTAG line to hard-reset the TAP controller """ self._ftdi = Ftdi() self._trst = trst self._frequency = frequency self.direction = JtagController.TCK_BIT | \ JtagController.TDI_BIT | \ JtagController.TMS_BIT | \ (self._trst and JtagController.TRST_BIT or 0) self._last = None # Last deferred TDO bit self._write_buff = Array('B') def __del__(self): self.close() # Public API def configure(self, vendor, product, interface): """Configure the FTDI interface as a JTAG controller""" curfreq = self._ftdi.open_mpsse( vendor, product, interface, direction=self.direction, #initial=0x0, frequency=self._frequency) # FTDI requires to initialize all GPIOs before MPSSE kicks in cmd = Array('B', [Ftdi.SET_BITS_LOW, 0x0, self.direction]) self._ftdi.write_data(cmd) def close(self): if self._ftdi: self._ftdi.close() self._ftdi = None def purge(self): self._ftdi.purge_buffers() def reset(self, sync=False): """Reset the attached TAP controller. sync sends the command immediately (no caching) """ # we can either send a TRST HW signal or perform 5 cycles with TMS=1 # to move the remote TAP controller back to 'test_logic_reset' state # do both for now if not self._ftdi: raise JtagError("FTDI controller terminated") if self._trst: # nTRST value = 0 cmd = Array('B', [Ftdi.SET_BITS_LOW, value, self.direction]) self._ftdi.write_data(cmd) time.sleep(0.1) # nTRST should be left to the high state value = JtagController.TRST_BIT cmd = Array('B', [Ftdi.SET_BITS_LOW, value, self.direction]) self._ftdi.write_data(cmd) time.sleep(0.1) # TAP reset (even with HW reset, could be removed though) self.write_tms(BitSequence('11111')) if sync: self.sync() def sync(self): if not self._ftdi: raise JtagError("FTDI controller terminated") if self._write_buff: self._ftdi.write_data(self._write_buff) self._write_buff = Array('B') def write_tms(self, tms): """Change the TAP controller state""" if not isinstance(tms, BitSequence): raise JtagError('Expect a BitSequence') length = len(tms) if not (0 < length < 8): raise JtagError('Invalid TMS length') out = BitSequence(tms, length=8) # apply the last TDO bit if self._last is not None: out[7] = self._last # print "TMS", tms, (self._last is not None) and 'w/ Last' or '' # reset last bit self._last = None cmd = Array('B', [Ftdi.WRITE_BITS_TMS_NVE, length - 1, out.tobyte()]) self._stack_cmd(cmd) self.sync() #self._ftdi.validate_mpsse() def read(self, length): """Read out a sequence of bits from TDO""" byte_count = length // 8 bit_count = length - 8 * byte_count bs = BitSequence() if byte_count: bytes = self._read_bytes(byte_count) bs.append(bytes) if bit_count: bits = self._read_bits(bit_count) bs.append(bits) return bs def write(self, out, use_last=True): """Write a sequence of bits to TDI""" if isinstance(out, str): if len(out) > 1: self._write_bytes_raw(out[:-1]) out = out[-1] out = BitSequence(bytes_=out) elif not isinstance(out, BitSequence): out = BitSequence(out) if use_last: (out, self._last) = (out[:-1], bool(out[-1])) byte_count = len(out) // 8 pos = 8 * byte_count bit_count = len(out) - pos if byte_count: self._write_bytes(out[:pos]) if bit_count: self._write_bits(out[pos:]) def shift_register(self, out, use_last=False): """Shift a BitSequence into the current register and retrieve the register output""" if not isinstance(out, BitSequence): return JtagError('Expect a BitSequence') length = len(out) if use_last: (out, self._last) = (out[:-1], int(out[-1])) byte_count = len(out) // 8 pos = 8 * byte_count bit_count = len(out) - pos if not byte_count and not bit_count: raise JtagError("Nothing to shift") if byte_count: blen = byte_count - 1 #print "RW OUT %s" % out[:pos] cmd = Array('B', [Ftdi.RW_BYTES_PVE_NVE_LSB, blen, (blen >> 8) & 0xff]) cmd.extend(out[:pos].tobytes(msby=True)) self._stack_cmd(cmd) #print "push %d bytes" % byte_count if bit_count: #print "RW OUT %s" % out[pos:] cmd = Array('B', [Ftdi.RW_BITS_PVE_NVE_LSB, bit_count - 1]) cmd.append(out[pos:].tobyte()) self._stack_cmd(cmd) #print "push %d bits" % bit_count self.sync() bs = BitSequence() byte_count = length // 8 pos = 8 * byte_count bit_count = length - pos if byte_count: data = self._ftdi.read_data_bytes(byte_count, 4) if not data: raise JtagError('Unable to read data from FTDI') byteseq = BitSequence(bytes_=data, length=8 * byte_count) #print "RW IN %s" % byteseq bs.append(byteseq) #print "pop %d bytes" % byte_count if bit_count: data = self._ftdi.read_data_bytes(1, 4) if not data: raise JtagError('Unable to read data from FTDI') byte = data[0] # need to shift bits as they are shifted in from the MSB in FTDI byte >>= 8 - bit_count bitseq = BitSequence(byte, length=bit_count) bs.append(bitseq) #print "pop %d bits" % bit_count if len(bs) != length: raise AssertionError("Internal error") #self._ftdi.validate_mpsse() return bs def _stack_cmd(self, cmd): if not isinstance(cmd, Array): raise TypeError('Expect a byte array') if not self._ftdi: raise JtagError("FTDI controller terminated") # Currrent buffer + new command + send_immediate if (len(self._write_buff) + len(cmd) + 1) >= JtagController.FTDI_PIPE_LEN: self.sync() self._write_buff.extend(cmd) def _read_bits(self, length): """Read out bits from TDO""" data = '' if length > 8: raise JtagError("Cannot fit into FTDI fifo") cmd = Array('B', [Ftdi.READ_BITS_NVE_LSB, length - 1]) self._stack_cmd(cmd) self.sync() data = self._ftdi.read_data_bytes(1, 4) # need to shift bits as they are shifted in from the MSB in FTDI byte = ord(data) >> 8 - bit_count bs = BitSequence(byte, length=length) #print "READ BITS %s" % (bs) return bs def _write_bits(self, out): """Output bits on TDI""" length = len(out) byte = out.tobyte() #print "WRITE BITS %s" % out cmd = Array('B', [Ftdi.WRITE_BITS_NVE_LSB, length - 1, byte]) self._stack_cmd(cmd) def _read_bytes(self, length): """Read out bytes from TDO""" data = '' if length > JtagController.FTDI_PIPE_LEN: raise JtagError("Cannot fit into FTDI fifo") alen = length - 1 cmd = Array('B', [Ftdi.READ_BYTES_NVE_LSB, alen & 0xff, (alen >> 8) & 0xff]) self._stack_cmd(cmd) self.sync() data = self._ftdi.read_data_bytes(length, 4) bs = BitSequence(bytes_=data, length=8 * length) #print "READ BYTES %s" % bs return bs def _write_bytes(self, out): """Output bytes on TDI""" bytes_ = out.tobytes(msby=True) # don't ask... olen = len(bytes_) - 1 #print "WRITE BYTES %s" % out cmd = Array( 'B', [Ftdi.WRITE_BYTES_NVE_LSB, olen & 0xff, (olen >> 8) & 0xff]) cmd.extend(bytes_) self._stack_cmd(cmd) def _write_bytes_raw(self, out): """Output bytes on TDI""" olen = len(out) - 1 cmd = Array( 'B', [Ftdi.WRITE_BYTES_NVE_LSB, olen & 0xff, (olen >> 8) & 0xff]) cmd.fromstring(out) self._stack_cmd(cmd)
class SpiController(object): """SPI master. :param silent_clock: should be set to avoid clocking out SCLK when all /CS signals are released. This clock beat is used to enforce a delay between /CS signal activation. When weird SPI devices are used, SCLK beating may cause trouble. In this case, silent_clock should be set but beware that SCLK line should be fitted with a pull-down resistor, as SCLK is high-Z during this short period of time. :param cs_count: is the number of /CS lines (one per device to drive on the SPI bus) """ SCK_BIT = 0x01 DO_BIT = 0x02 DI_BIT = 0x04 CS_BIT = 0x08 PAYLOAD_MAX_LENGTH = 0x10000 # 16 bits max def __init__(self, silent_clock=False, cs_count=4): self._ftdi = Ftdi() self._cs_bits = ((SpiController.CS_BIT << cs_count) - 1) & \ ~(SpiController.CS_BIT - 1) self._ports = [None] * cs_count self._direction = self._cs_bits | \ SpiController.DO_BIT | \ SpiController.SCK_BIT self._cs_high = Array('B') if silent_clock: # Set SCLK as input to avoid emitting clock beats self._cs_high.extend([Ftdi.SET_BITS_LOW, self._cs_bits, self._direction & ~SpiController.SCK_BIT]) # /CS to SCLK delay, use 8 clock cycles as a HW tempo self._cs_high.extend([Ftdi.WRITE_BITS_TMS_NVE, 8-1, 0xff]) # Restore idle state self._cs_high.extend([Ftdi.SET_BITS_LOW, self._cs_bits, self._direction]) self._immediate = Array('B', [Ftdi.SEND_IMMEDIATE]) self._frequency = 0.0 def configure(self, vendor, product, interface, frequency=6.0E6): """Configure the FTDI interface as a SPI master""" self._frequency = \ self._ftdi.open_mpsse(vendor, product, interface, direction=self._direction, initial=self._cs_bits, # /CS all high frequency=frequency) def terminate(self): """Close the FTDI interface""" if self._ftdi: self._ftdi.close() self._ftdi = None def get_port(self, cs): """Obtain a SPI port to drive a SPI device selected by cs""" if not self._ftdi: raise SpiIOError("FTDI controller not initialized") if cs >= len(self._ports): raise SpiIOError("No such SPI port") if not self._ports[cs]: cs_state = 0xFF & ~((SpiController.CS_BIT<<cs) | SpiController.SCK_BIT | SpiController.DO_BIT) cs_cmd = Array('B', [Ftdi.SET_BITS_LOW, cs_state, self._direction]) self._ports[cs] = SpiPort(self, cs_cmd) self._flush() return self._ports[cs] @property def frequency_max(self): """Returns the maximum SPI clock""" return self._ftdi.frequency_max @property def frequency(self): """Returns the current SPI clock""" return self._frequency def _exchange(self, frequency, cs_cmd, out, readlen): """Perform a half-duplex transaction with the SPI slave""" if not self._ftdi: raise SpiIOError("FTDI controller not initialized") if len(out) > SpiController.PAYLOAD_MAX_LENGTH: raise SpiIOError("Output payload is too large") if readlen > SpiController.PAYLOAD_MAX_LENGTH: raise SpiIOError("Input payload is too large") if self._frequency != frequency: freq = self._ftdi.set_frequency(frequency) # store the requested value, not the actual one (best effort) self._frequency = frequency write_cmd = struct.pack('<BH', Ftdi.WRITE_BYTES_NVE_MSB, len(out)-1) if readlen: read_cmd = struct.pack('<BH', Ftdi.READ_BYTES_NVE_MSB, readlen-1) cmd = Array('B', cs_cmd) cmd.fromstring(write_cmd) cmd.extend(out) cmd.fromstring(read_cmd) cmd.extend(self._immediate) cmd.extend(self._cs_high) self._ftdi.write_data(cmd) # USB read cycle may occur before the FTDI device has actually # sent the data, so try to read more than once if no data is # actually received data = self._ftdi.read_data_bytes(readlen, 4) else: cmd = Array('B', cs_cmd) cmd.fromstring(write_cmd) cmd.extend(out) cmd.extend(self._cs_high) self._ftdi.write_data(cmd) data = Array('B') return data def _flush(self): """Flush the HW FIFOs""" self._ftdi.write_data(self._immediate) self._ftdi.purge_buffers()
class Dionysus(Olympus): """Dionysus Concrete Class that implements Dionysus specific communication functions """ def __init__(self, idVendor=0x0403, idProduct=0x8530, debug = False): Olympus.__init__(self, debug) self.vendor = idVendor self.product = idProduct self.dev = Ftdi() self._open_dev() self.name = "Dionysus" def __del__(self): self.dev.close() def _open_dev(self): """_open_dev Open an FTDI communication channel Args: Nothing Returns: Nothing Raises: Exception """ frequency = 30.0E6 #Latency can go down t 2 but when set there is a small chance that there is a crash latency = 4 self.dev.open(self.vendor, self.product, 0) # Drain input buffer self.dev.purge_buffers() # Reset # Enable MPSSE mode self.dev.set_bitmode(0x00, Ftdi.BITMODE_SYNCFF) # Configure clock frequency = self.dev._set_frequency(frequency) # Set latency timer self.dev.set_latency_timer(latency) # Set chunk size self.dev.write_data_set_chunksize(0x10000) self.dev.read_data_set_chunksize(0x10000) self.dev.set_flowctrl('hw') self.dev.purge_buffers() def read(self, device_id, address, length = 1, mem_device = False): """read read data from the Olympus image Args: device_id: Device identification number, found in the DRT address: Address of the register/memory to read mem_device: True if the device is on the memory bus length: Number of 32 bit words to read from the FPGA Returns: A byte array containing the raw data returned from Olympus Raises: OlympusCommError """ read_data = Array('B') write_data = Array('B', [0xCD, 0x02]) if mem_device: if self.debug: print "memory device" write_data = Array ('B', [0xCD, 0x12]) fmt_string = "%06X" % (length) write_data.fromstring(fmt_string.decode('hex')) offset_string = "00" if not mem_device: offset_string = "%02X" % device_id write_data.fromstring(offset_string.decode('hex')) addr_string = "%06X" % address write_data.fromstring(addr_string.decode('hex')) if self.debug: print "data read string: " + str(write_data) self.dev.purge_buffers() self.dev.write_data(write_data) timeout = time.time() + self.read_timeout rsp = Array('B') while time.time() < timeout: response = self.dev.read_data(1) if len(response) > 0: rsp = Array('B') rsp.fromstring(response) if rsp[0] == 0xDC: if self.debug: print "Got a response" break if len(rsp) > 0: if rsp[0] != 0xDC: if self.debug: print "Response not found" raise OlympusCommError("Did not find identification byte (0xDC): %s" % str(rsp)) else: if self.debug: print "No Response found" raise OlympusCommError("Timeout while waiting for a response") #I need to watch out for the modem status bytes read_count = 0 response = Array('B') rsp = Array('B') timeout = time.time() + self.read_timeout while (time.time() < timeout) and (read_count < (length * 4 + 8)): response = self.dev.read_data((length * 4 + 8 ) - read_count) temp = Array('B') temp.fromstring(response) #print "temp: %s", str(temp) if (len(temp) > 0): rsp += temp read_count = len(rsp) if self.debug: print "read length = %d, total length = %d" % (len(rsp), (length * 4 + 8)) print "time left on timeout: %d" % (timeout - time.time()) if self.debug: print "response length: " + str(length * 4 + 8) print "response status:\n\t" + str(rsp[:8]) print "response data:\n" + str(rsp[8:]) return rsp[8:] def write(self, device_id, address, data=None, mem_device = False): """write Write data to an Olympus image Args: device_id: Device identification number, found in the DRT address: Address of the register/memory to read mem_device: True if the device is on the memory bus data: Array of raw bytes to send to the device Returns: Nothing Raises: OlympusCommError """ length = len(data) / 4 # ID 01 NN NN NN OO AA AA AA DD DD DD DD # ID = ID BYTE (0xCD) # 01 = Write Command # NN = Size of write (3 bytes) # OO = Offset of device # AA = Address (4 bytes) # DD = Data (4 bytes) #create an array with the identification byte (0xCD) #and code for write (0x01) data_out = Array('B', [0xCD, 0x01]) if mem_device: if self.debug: print "memory device" data_out = Array ('B', [0xCD, 0x11]) """ print "write command:\n\t" + str(data_out[:9]) for i in range (0, len(data_out)): print str(hex(data_out[i])) + ", ", print " " """ #append the length into the frist 32 bits fmt_string = "%06X" % (length) data_out.fromstring(fmt_string.decode('hex')) offset_string = "00" if not mem_device: offset_string = "%02X" % device_id data_out.fromstring(offset_string.decode('hex')) addr_string = "%06X" % address data_out.fromstring(addr_string.decode('hex')) data_out.extend(data) """ #if (self.debug): print "data write string:\n" print "write command:\n\t" + str(data_out[:9]) for i in range (0, 9): print str(hex(data_out[i])) + ", ", print " " """ #print "write data:\n" + str(data_out[9:]) #avoid the akward stale bug self.dev.purge_buffers() self.dev.write_data(data_out) rsp = Array('B') timeout = time.time() + self.read_timeout while time.time() < timeout: response = self.dev.read_data(1) if len(response) > 0: rsp = Array('B') rsp.fromstring(response) if rsp[0] == 0xDC: if self.debug: print "Got a response" break if (len(rsp) > 0): if rsp[0] != 0xDC: if self.debug: print "Response not found" raise OlympusCommError("Did not find identification byte (0xDC): %s" % str(rsp)) else: if self.debug: print "No Response" raise OlympusCommError("Timeout while waiting for a response") response = self.dev.read_data(8) rsp = Array('B') rsp.fromstring(response) if self.debug: print "Response: " + str(rsp) def ping(self): """ping Pings the Olympus image Args: Nothing Returns: Nothing Raises: OlympusCommError """ data = Array('B') data.extend([0XCD, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00]); if self.debug: print "Sending ping...", self.dev.write_data(data) rsp = Array('B') temp = Array('B') timeout = time.time() + self.read_timeout while time.time() < timeout: response = self.dev.read_data(5) if self.debug: print ".", rsp = Array('B') rsp.fromstring(response) temp.extend(rsp) if 0xDC in rsp: if self.debug: print "Got a response" print "Response: %s" % str(temp) break if not 0xDC in rsp: if self.debug: print "ID byte not found in response" print "temp: " + str(temp) raise OlympusCommError("Ping response did not contain ID: %s" % str(temp)) index = rsp.index(0xDC) + 1 read_data = Array('B') read_data.extend(rsp[index:]) num = 3 - index read_data.fromstring(self.dev.read_data(num)) if self.debug: print "Success!" return def reset(self): """reset Software reset the Olympus FPGA Master, this may not actually reset the entire FPGA image Args: Nothing Returns: Nothing Raises: OlympusCommError: A failure of communication is detected """ data = Array('B') data.extend([0XCD, 0x03, 0x00, 0x00, 0x00]); if self.debug: print "Sending reset..." self.dev.purge_buffers() self.dev.write_data(data) def dump_core(self): """dump_core reads the state of the wishbone master prior to a reset, useful for debugging Args: Nothing Returns: Array of 32-bit values to be parsed by core_analyzer Raises: AssertionError: This function must be overriden by a board specific implementation OlympusCommError: A failure of communication is detected """ data = Array('B') data.extend([0xCD, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00]); print "Sending core dump request..." self.dev.purge_buffers() self.dev.write_data(data) core_dump = Array('L') wait_time = 5 timeout = time.time() + wait_time temp = Array ('B') while time.time() < timeout: response = self.dev.read_data(1) rsp = Array('B') rsp.fromstring(response) temp.extend(rsp) if 0xDC in rsp: print "Got a response" break if not 0xDC in rsp: print "Response not found" raise OlympusCommError("Response Not Found") rsp = Array('B') read_total = 4 read_count = len(rsp) #get the number of items from the address timeout = time.time() + wait_time while (time.time() < timeout) and (read_count < read_total): response = self.dev.read_data(read_total - read_count) temp = Array('B') temp.fromstring(response) if (len(temp) > 0): rsp += temp read_count = len(rsp) print "Length of read: %d" % len(rsp) print "Data: %s" % str(rsp) count = ( rsp[1] << 16 | rsp[2] << 8 | rsp[3]) * 4 print "Number of core registers: %d" % (count / 4) #get the core dump data timeout = time.time() + wait_time read_total = count read_count = 0 temp = Array ('B') rsp = Array('B') while (time.time() < timeout) and (read_count < read_total): response = self.dev.read_data(read_total - read_count) temp = Array('B') temp.fromstring(response) if (len(temp) > 0): rsp += temp read_count = len(rsp) print "Length read: %d" % (len(rsp) / 4) print "Data: %s" % str(rsp) core_data = Array('L') for i in range (0, count, 4): print "count: %d" % i core_data.append(rsp[i] << 24 | rsp[i + 1] << 16 | rsp[i + 2] << 8 | rsp[i + 3]) #if self.debug: print "core data: " + str(core_data) return core_data def wait_for_interrupts(self, wait_time = 1): """wait_for_interrupts listen for interrupts for the specified amount of time Args: wait_time: the amount of time in seconds to wait for an interrupt Returns: True: Interrupts were detected False: No interrupts detected Raises: Nothing """ timeout = time.time() + wait_time temp = Array ('B') while time.time() < timeout: response = self.dev.read_data(1) rsp = Array('B') rsp.fromstring(response) temp.extend(rsp) if 0xDC in rsp: if self.debug: print "Got a response" break if not 0xDC in rsp: if self.debug: print "Response not found" return False read_total = 9 read_count = len(rsp) #print "read_count: %s" % str(rsp) while (time.time() < timeout) and (read_count < read_total): response = self.dev.read_data(read_total - read_count) temp = Array('B') temp.fromstring(response) #print "temp: %s", str(temp) if (len(temp) > 0): rsp += temp read_count = len(rsp) #print "read_count: %s" % str(rsp) index = rsp.index(0xDC) + 1 read_data = Array('B') read_data.extend(rsp[index:]) #print "read_data: " + str(rsp) self.interrupts = read_data[-4] << 24 | read_data[-3] << 16 | read_data[-2] << 8 | read_data[-1] if self.debug: print "interrupts: " + str(self.interrupts) return True def comm_debug(self): """comm_debug A function that the end user will probably not interract with This is here to simply debug a communication medium Args: Nothing Returns: Nothing Raises: Nothing """ #self.dev.set_dtr_rts(True, True) #self.dev.set_dtr(False) print "CTS: " + str(self.dev.get_cts()) # print "DSR: " + str(self.dev.get_dsr()) s1 = self.dev.modem_status() print "S1: " + str(s1)