def rlca(cpu, opcode, logger):
cflag = Bits.getNthBit(cpu.A, 7)
cpu.A = Bits.setNthBit(cpu.A << 1, 0, cflag)
cpu.CFlag = Bits.set() if cflag != 0 else Bits.reset()
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("RLCA")
def test_jr_z_does_not_change_the_z_flag(self):
cpu = CPU(ROM('\x28\x00\x28\x00'))
cpu.ZFlag = Bits.reset()
cpu.readOp()
self.assertFalse(cpu.ZFlag)
cpu.ZFlag = Bits.set()
cpu.readOp()
self.assertTrue(cpu.ZFlag)
def cpl(cpu, opcode, logger):
old = cpu.A
new = ~old
cpu.A = new
cpu.HFlag = Bits.set()
cpu.NFlag = Bits.set()
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("CPL")
def dec_at_hl(cpu, opcode, logger):
old_val = cpu.ram[cpu.HL]
new_val = old_val - 1
cpu.ram[cpu.HL] = new_val
cpu.ZFlag = Bits.isZero(new_val)
cpu.SFlag = Bits.isNegative(new_val)
cpu.NFlag = Bits.set()
cpu.PVFlag = Bits.halfCarrySub(old_val, new_val)
cpu.m_cycles, cpu.t_states = 3, 11
logger.info("DEC (HL)")
def _and(cpu, opcode, logger):
logger.info("AND A")
regInd = opcode & 7
cpu.A = cpu.A & cpu.regs[regInd]
cpu.flags[HF] = True
cpu.flags[CF] = False
cpu.flags[NF] = False
cpu.flags[ZF] = Bits.isZero(cpu.A)
cpu.flags[SF] = Bits.signInTwosComp(cpu.A)
cpu.flags[PVF] = Bits.paritySet(cpu.A)
def _checkInterrupts(self):
if self.iff1:
self.halted = Bits.reset()
self.iff1 = Bits.reset()
self.iff2 = Bits.reset()
self.ram[--self.SP] = Bits.limitTo8Bits(self.pc)
self.ram[--self.SP] = self.pc >> 8
self.R += 1
if self.im == 0 or self.im == 1:
self.PC = 0x0038
def test_ed43nn_does_not_affect_flags(self):
cpu = CPU(ROM(b'\xed\x43\x00\x10'))
cpu.CFlag = Bits.set()
cpu.ZFlag = Bits.reset()
cpu.SFlag = Bits.set()
cpu.HFlag = Bits.reset()
cpu.readOp()
self.assertTrue(cpu.CFlag)
self.assertFalse(cpu.ZFlag)
self.assertTrue(cpu.SFlag)
self.assertFalse(cpu.HFlag)
def test_ld_nn_a_does_not_affect_flags(self):
cpu = CPU(ROM(b'\x32\xb2\x29'))
cpu.HFlag = Bits.reset()
cpu.ZFlag = Bits.set()
cpu.PVFlag = Bits.reset()
cpu.SFlag = Bits.set()
self.assertFalse(cpu.HFlag)
self.assertTrue(cpu.ZFlag)
self.assertFalse(cpu.PVFlag)
self.assertTrue(cpu.SFlag)
def dec_at_ix_d(cpu, opcode, logger):
d = cpu.ram[cpu.PC]
old_val = cpu.ram[cpu.IX+d]
new_val = old_val - 1
cpu.ram[cpu.IX+d] = new_val
cpu.ZFlag = Bits.isZero(new_val)
cpu.SFlag = Bits.isNegative(new_val)
cpu.NFlag = Bits.set()
cpu.PVFlag = Bits.halfCarrySub(old_val, new_val)
cpu.m_cycles, cpu.t_states = 6, 23
logger.info("DEC (IX+{:02X})".format(d))
def _checkInterrupts(self):
if self.iff1 and self.generateInterrupt:
self.generateInterrupt = False
self.halted = Bits.reset()
self.iff1 = Bits.reset()
self.iff2 = Bits.reset()
self.ram[--self.SP] = Bits.limitTo8Bits(self.pc)
self.ram[--self.SP] = self.pc >> 8
self.R += 1
if self.im == 0 or self.im == 1:
self.PC = 0x0038
def inc8(cpu, opcode, logger):
logger.info("INC r")
index = ( opcode >> 3 ) & 7
oldValue = cpu.regs[index]
cpu.regs[index] = (cpu.regs[index] + 1 ) & 0xFF
cpu.NFlag = False
cpu.ZFlag = Bits.isZero(cpu.regs[index])
cpu.HFlag = Bits.halfCarrySub(oldValue, cpu.regs[index])
cpu.PVFlag = True if oldValue == 0x7f else False
cpu.SFlag = Bits.twos_comp(cpu.regs[index]) < 0
def add_iy_rr(cpu, opcode, logger):
regInd = (opcode >> 4) & 3
val = cpu.Reg16(regInd, iy=True)
old = cpu.IY
cpu.IY = cpu.IY + val
cpu.NFlag = Bits.reset()
cpu.HFlag = Bits.carryFlagAdd16(old, cpu.IY)
cpu.CFlag = Bits.overflow(old, cpu.IY, bits=16)
cpu.m_cycles, cpu.t_states = 4, 15
logger.info("ADD IY, {}".format(IndexToReg.translate16Bit(regInd)))
def adc_r(cpu, opcode, logger):
reg_idx = (opcode & 7)
old_val = cpu.A
cpu.A = old_val + cpu.regs[reg_idx] + (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.NFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("ADC A, {}".format(IndexToReg.translate8Bit(reg_idx)))
def xorA(cpu, opcode, logger):
"""XOR A"""
regInd = opcode & 7
cpu.A = cpu.A ^ cpu.regs[regInd]
"""Flags"""
cpu.flags[ZF] = Bits.isZero(cpu.A)
cpu.flags[CF] = False
cpu.flags[NF] = False
cpu.flags[HF] = False
cpu.flags[SF] = Bits.signInTwosComp(cpu.A)
cpu.flags[PVF] = Bits.paritySet(cpu.A)
logger.info("XOR A")
def cp(cpu, opcode, logger):
regInd = opcode & 7
logger.info(regInd)
value = cpu.A - cpu.regs[regInd]
"""Flags"""
cpu.flags[ZF] = Bits.isZero(value)
cpu.flags[CF] = Bits.carryFlag(value)
cpu.flags[NF] = True
cpu.flags[HF] = Bits.halfCarrySub(cpu.A, value)
cpu.flags[SF] = Bits.signFlag(value)
cpu.flags[PVF] = Bits.overflow(cpu.A, value)
logger.info("CP r")
def sub_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
value = cpu.A - n
cpu.NFlag = Bits.set()
cpu.ZFlag = Bits.isZero(value)
cpu.HFlag = Bits.halfCarrySub(cpu.A, value)
cpu.PVFlag = Bits.overflow(cpu.A, value)
cpu.CFlag = Bits.carryFlag(value)
cpu.A = value
logger.info("SUB {:02X}".format(n))
def add16(cpu, opcode, logger):
regInd = (opcode & 0x30) >> 4
value = cpu.Reg16(regInd)
oldHL = cpu.HL
cpu.HL = cpu.HL + value
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.carryFlag16(oldHL, cpu.HL)
cpu.HFlag = Bits.carryFlag16(oldHL, cpu.HL, bits=11)
cpu.m_cycles, cpu.t_states = 3, 11
logger.info("ADD HL, {}".format(IndexToReg.translate16Bit(regInd)))
def dec8b(cpu, opcode, logger):
reg_index = (opcode >> 3) & 7
old_val = cpu.regs[reg_index]
cpu.regs[reg_index] = cpu.regs[reg_index] - 1
cpu.ZFlag = Bits.isZero(cpu.regs[reg_index])
cpu.SFlag = Bits.isNegative(cpu.regs[reg_index])
cpu.NFlag = Bits.set()
cpu.PVFlag = Bits.halfCarrySub(old_val, cpu.regs[reg_index])
cpu.HFlag = Bits.halfCarrySub(old_val, cpu.regs[reg_index])
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("DEC {}".format(IndexToReg.translate8Bit(reg_index)))
def inc8(cpu, opcode, logger):
index = (opcode >> 3) & 7
oldValue = cpu.regs[index]
cpu.regs[index] = Bits.limitTo8Bits(cpu.regs[index] + 1)
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.regs[index])
cpu.HFlag = Bits.halfCarrySub(oldValue, cpu.regs[index])
cpu.PVFlag = True if oldValue == 0x7f else False
cpu.SFlag = Bits.isNegative(cpu.regs[index])
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("INC {}".format(IndexToReg.translate8Bit(index)))
def dec_mem_at_iy(cpu, opcode, logger):
displacement = cpu.ram[cpu.PC]
addr = cpu.IY + displacement
value = cpu.ram[addr]
new_value = value - 1
cpu.ram[addr] = new_value
cpu.NFlag = Bits.set()
cpu.SFlag = Bits.isNegative(new_value)
cpu.ZFlag = Bits.isZero(new_value)
cpu.PVFlag = True if value == 0x80 else False
cpu.HFlag = Bits.halfCarrySub(value, new_value)
logger.info("DEC (IY+{:2X})".format(displacement))
def rrd(cpu, opcode, logger):
low_a = cpu.A & 0x0F
mem_hl = cpu.ram[cpu.HL]
low_hl = mem_hl & 0x0F
high_hl = (mem_hl & 0xF0) >> 4
cpu.A = (cpu.A & 0xF0) | low_hl
mem_hl = (low_a << 4) | high_hl
cpu.ram[cpu.HL] = mem_hl
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.HFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 5, 18
logger.info("RRD")
def test_add_a_l_with_C_flag_reset_correctly_caluclates_value(self):
cpu = CPU(ROM(b'\x8d'))
cpu.A = 0x22
cpu.L = 0x44
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(0x66, cpu.A)
def test_add_HL_BC_with_C_flag_unset_correctly_calculates_value(self):
cpu = CPU(ROM('\xed\x4a'))
cpu.HL = 0xCDCD
cpu.BC = 0x1111
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(0XCDCD+0x1111, cpu.HL)
def test_add_a_e_with_C_flag_set_correctly_caluclates_value(self):
cpu = CPU(ROM('\x8b'))
cpu.A = 0x22
cpu.E = 0x66
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(0x89, cpu.A)
def test_jr_z_jumps_if_ZFlag_is_set(self):
rom = '\x00' * 0x0300+'\x28\x03'
cpu = CPU(ROM(rom))
cpu.PC = 0x0300
cpu.ZFlag = Bits.set()
cpu.readOp()
self.assertEqual(0x0305, cpu.PC)
def test_sbc_a_mem_hl_correctly_calculates_value(self):
cpu = CPU(ROM(b'\x9e\x00\x00\x22'))
cpu.A = 0x23
cpu.HL = 0x3
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(0, cpu.A)
def test_sbc_a_d_sets_SFlag_when_result_is_below_zero(self):
cpu = CPU(ROM(b'\x9a'))
cpu.A = 0x40
cpu.D = 0x44
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertTrue(cpu.SFlag)
def test_sbc_a_b_correctly_calculates_result(self):
cpu = CPU(ROM(b'\x98'))
cpu.A = 0x40
cpu.B = 0x3f
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(0, cpu.A)
def test_add_a_b_with_C_flag_reset_correctly_calculates_value(self):
cpu = CPU(ROM(b'\x88'))
cpu.A = 0x22
cpu.B = 0x33
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(0x55, cpu.A)
def test_add_HL_SP_with_C_flag_set_correctly_calculates_value(self):
cpu = CPU(ROM(b'\xed\x7a'))
cpu.HL = 0x1111
cpu.SP = 0x2222
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(0x1111 + 0x2222 + 0x1, cpu.HL)
def lddr(cpu, opcode, logger):
isZero = cpu.BC == 0
while True:
cpu.ram[cpu.DE] = cpu.ram[cpu.HL]
cpu.HL = cpu.HL - 1
cpu.DE = cpu.DE - 1
cpu.BC = cpu.BC - 1
if cpu.BC == 0:
cpu.NFlag = Bits.reset()
cpu.HFlag = Bits.reset()
cpu.PVFlag = Bits.reset()
break
cpu.m_cycles, cpu.t_states = 4 if isZero else 5, 16 if isZero else 21
logger.info("LDDR")
def test_adc_A_mem_HL_with_CFlag_set_correctly_sets_A_register(self):
cpu = CPU(ROM(b'\x8e\x15\x16\x17\x18'))
cpu.HL = 0x03
cpu.A = 0x5
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(0x1d, cpu.A)
def test_add_HL_BC_with_C_flag_unset_takes_15_t_states(self):
cpu = CPU(ROM(b'\xed\x4a'))
cpu.HL = 0xCDCD
cpu.BC = 0x1111
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(15, cpu.t_states)
def test_add_a_b_with_C_flag_set_takes_4_t_states(self):
cpu = CPU(ROM(b'\x88'))
cpu.A = 0x12
cpu.B = 0x12
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(4, cpu.t_states)
def test_jp_nz_jumps_takes_3_m_cycles_if_jump_is_taken(self):
rom = '\x00' * 0x0480+'\x20\xFA'
cpu = CPU(ROM(rom))
cpu.PC = 0x0480
cpu.ZFlag = Bits.reset()
cpu.readOp()
self.assertEqual(3, cpu.m_cycles)
def test_jp_nz_jumps_takes_7_t_states_if_jump_is_taken(self):
rom = '\x00' * 0x0480+'\x20\xFA'
cpu = CPU(ROM(rom))
cpu.PC = 0x0480
cpu.ZFlag = Bits.set()
cpu.readOp()
self.assertEqual(7, cpu.t_states)
def test_add_a_c_with_C_flag_reset_correctly_caluclates_value(self):
cpu = CPU(ROM(b'\x89'))
cpu.A = 0x22
cpu.C = 0x88
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(0xAA, cpu.A)
def test_sbc_a_c_without_c_calculates_results(self):
cpu = CPU(ROM(b'\x99'))
cpu.A = 0x40
cpu.C = 0x3f
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(1, cpu.A)
def test_add_a_d_with_C_flag_reset_correctly_caluclates_value(self):
cpu = CPU(ROM(b'\x8a'))
cpu.A = 0x22
cpu.D = 0x77
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(0x99, cpu.A)
def test_sbc_a_e_sets_ZFlag_when_result_is_zero(self):
cpu = CPU(ROM(b'\x9b'))
cpu.A = 0x44
cpu.E = 0x44
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertTrue(cpu.ZFlag)
def test_jp_nz_jumps_takes_3_m_cycles_if_jump_is_taken(self):
rom = b'\x00' * 0x0480 + b'\x20\xFA'
cpu = CPU(ROM(rom))
cpu.PC = 0x0480
cpu.ZFlag = Bits.reset()
cpu.readOp()
self.assertEqual(3, cpu.m_cycles)
def test_add_iy_rr_resets_n_flag(self):
cpu = CPU(ROM(b'\xfd\x39'))
cpu.IY = 0x1001
cpu.SP = 0x0880
cpu.NFlag = Bits.set()
cpu.readOp()
self.assertFalse(cpu.NFlag)
def test_add_a_e_with_C_flag_set_correctly_caluclates_value(self):
cpu = CPU(ROM(b'\x8b'))
cpu.A = 0x22
cpu.E = 0x66
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(0x89, cpu.A)
def test_add_iy_rr_resets_n_flag(self):
cpu = CPU(ROM('\xfd\x39'))
cpu.IY = 0x1001
cpu.SP = 0x0880
cpu.NFlag = Bits.set()
cpu.readOp()
self.assertFalse(cpu.NFlag)
def jpnc(cpu, opcode, logger):
jumpOffset = Bits.twos_comp(cpu.rom.readMemory(cpu.PC)) - 2
if cpu.CFlag:
return
cpu.PC = cpu.PC + jumpOffset
logger.info("JP NC {0:x}".format(jumpOffset))
def test_add_a_d_with_C_flag_reset_correctly_caluclates_value(self):
cpu = CPU(ROM('\x8a'))
cpu.A = 0x22
cpu.D = 0x77
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(0x99, cpu.A)
def jpnz(cpu, opcode, logger):
jumpOffset = cpu.rom.readMemory(cpu.PC)
if cpu.ZFlag:
return
cpu.PC = cpu.PC + Bits.twos_comp(jumpOffset)
logger.info("JPNZ {0:x}".format(jumpOffset))
def test_adc_A_mem_HL_takes_7_t_states(self):
cpu = CPU(ROM(b'\x8e\x05\x06\x07\x08'))
cpu.HL = 0x03
cpu.A = 0x5
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(7, cpu.t_states)
def test_add_a_h_with_C_flag_set_correctly_caluclates_value(self):
cpu = CPU(ROM(b'\x8c'))
cpu.A = 0x22
cpu.H = 0x55
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(0x78, cpu.A)
def ldir(cpu, opcode, logger):
wasZero = cpu.BC == 0
while True:
hl_mem = cpu.ram[cpu.HL]
cpu.ram[cpu.DE] = hl_mem
cpu.HL = cpu.HL + 1
cpu.DE = cpu.DE + 1
cpu.BC = cpu.BC - 1
if cpu.BC == 0:
break
cpu.NFlag = Bits.reset()
cpu.HFlag = Bits.reset()
cpu.PVFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 4 if wasZero else 5, 16 if wasZero else 21
logger.info("LDIR")
def test_add_HL_DE_with_C_flag_set_correctly_calculates_value(self):
cpu = CPU(ROM(b'\xed\x5a'))
cpu.HL = 0xCDCD
cpu.DE = 0x1111
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(0XCDCD + 0x1111 + 0x1, cpu.HL)
def test_add_HL_BC_with_C_flag_unset_correctly_calculates_value(self):
cpu = CPU(ROM(b'\xed\x4a'))
cpu.HL = 0xCDCD
cpu.BC = 0x1111
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(0XCDCD + 0x1111, cpu.HL)
def test_jp_nz_jumps_takes_7_t_states_if_jump_is_taken(self):
rom = b'\x00' * 0x0480 + b'\x20\xFA'
cpu = CPU(ROM(rom))
cpu.PC = 0x0480
cpu.ZFlag = Bits.set()
cpu.readOp()
self.assertEqual(7, cpu.t_states)
def jr_e(cpu, opcode, logger):
pc = cpu.PC
jumpOffset = Bits.twos_comp(cpu.ram[pc])
cpu.PC = pc + jumpOffset + 1
cpu.m_cycles, cpu.t_states = 3, 12
logger.info("JR {0:x}".format(jumpOffset))
def test_bit_IY_plus_4_set_correctly_set_z_flag(self):
ram = RAM()
ram[0x2004] = 0b10111111
cpu = CPU(ROM(b'\xfd\xcb\x04\x76'), ram)
cpu.ZFlag = Bits.reset()
cpu.IY = 0x2000
cpu.readOp()
self.assertTrue(cpu.ZFlag)
def test_bit_IY_plus_4_takes_20_t_states(self):
ram = RAM()
ram[0x2004] = 1 << 6
cpu = CPU(ROM(b'\xfd\xcb\x04\x76'), ram)
cpu.ZFlag = Bits.reset()
cpu.IY = 0x2000
cpu.readOp()
self.assertEqual(20, cpu.t_states)
def test_ret_cc_does_takes_3_m_cycles_if_cc_is_true(self):
ram = RAM()
ram[0x4000] = 0xB5
ram[0x4001] = 0x18
cpu = CPU(ROM(b'\x00' * 0x3535 + b'\xf0'), ram)
cpu.PC = 0x3535
cpu.SP = 0x4000
cpu.SFlag = Bits.reset()
cpu.readOp()
self.assertEqual(3, cpu.m_cycles)
def test_ret_cc_does_takes_5_t_states_if_cc_is_false(self):
ram = RAM()
ram[0x4000] = 0xB5
ram[0x4001] = 0x18
cpu = CPU(ROM(b'\x00' * 0x3535 + b'\xf0'), ram)
cpu.PC = 0x3535
cpu.SP = 0x4000
cpu.SFlag = Bits.set()
cpu.readOp()
self.assertEqual(5, cpu.t_states)
def test_call_cc_takes_5_m_cycles_if_condition_is_true(self):
ram = RAM()
rom = ROM(b'\x00' * 0x1A47 + b'\xDC\x35\x21')
cpu = CPU(rom, ram)
cpu.PC = 0x1A47
cpu.SP = 0x3002
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(5, cpu.m_cycles)
def test_call_cc_takes_10_t_cycles_if_condition_is_false(self):
ram = RAM()
rom = ROM(b'\x00' * 0x1A47 + b'\xDC\x35\x21')
cpu = CPU(rom, ram)
cpu.PC = 0x1A47
cpu.SP = 0x3002
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(10, cpu.t_states)
