def sbc(cpu, opcode, logger):
logger.info("SBC HL")
regInd = (opcode & 0x30) >> 4
value = 0
if regInd == 0:
value = cpu.BC
elif regInd == 1:
value = cpu.DE
elif regInd == 2:
value = cpu.HL
elif regInd == 3:
value = cpu.SP
oldHL = cpu.HL
logger.info("Old value of HL: " + str(oldHL))
cpu.HL = cpu.HL - value - (1 if cpu.CFlag else 0)
logger.info("New value of HL: " + str(cpu.HL))
cpu.flags[SF] = Bits.signFlag(cpu.HL, bits=16)
cpu.flags[ZF] = Bits.isZero(cpu.HL)
cpu.flags[HF] = Bits.halfCarrySub16(oldHL, cpu.HL)
cpu.flags[PVF] = Bits.overflow(Bits.twos_comp(oldHL, bits=16),
Bits.twos_comp(cpu.HL, bits=16))
cpu.flags[NF] = True
cpu.flags[CF] = Bits.borrow(cpu.HL, bits=16)
def cp_hl(cpu, opcode, logger):
value = cpu.A - cpu.ram[cpu.HL]
cpu.ZFlag = Bits.isZero(value)
cpu.CFlag = Bits.carryFlag(value)
cpu.NFlag = Bits.set()
cpu.HFlag = Bits.halfCarrySub(cpu.A, value)
cpu.SFlag = Bits.signFlag(value)
cpu.PVFlag = Bits.overflow(value, cpu.A)
cpu.m_cycles, cpu.t_states = 1, 7
logger.info("CP (HL)")
def cp(cpu, opcode, logger):
regInd = opcode & 7
value = cpu.A - cpu.regs[regInd]
cpu.ZFlag = Bits.isZero(value)
cpu.CFlag = Bits.carryFlag(value)
cpu.NFlag = Bits.set()
cpu.HFlag = Bits.halfCarrySub(cpu.A, value)
cpu.SFlag = Bits.signFlag(value)
cpu.PVFlag = Bits.overflow(value, cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("CP {}".format(IndexToReg.translate8Bit(regInd)))
def add_iy_rr(cpu, opcode, logger):
regInd = (opcode >> 4) & 3
val = cpu.Reg16(regInd, iy=True)
old = cpu.IY
cpu.IY = cpu.IY + val
cpu.NFlag = Bits.reset()
cpu.HFlag = Bits.carryFlagAdd16(old, cpu.IY)
cpu.CFlag = Bits.overflow(old, cpu.IY, bits=16)
cpu.m_cycles, cpu.t_states = 4, 15
logger.info("ADD IY, {}".format(IndexToReg.translate16Bit(regInd)))
def sub_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
value = cpu.A - n
cpu.NFlag = Bits.set()
cpu.ZFlag = Bits.isZero(value)
cpu.HFlag = Bits.halfCarrySub(cpu.A, value)
cpu.PVFlag = Bits.overflow(cpu.A, value)
cpu.CFlag = Bits.carryFlag(value)
cpu.A = value
logger.info("SUB {:02X}".format(n))
def cp(cpu, opcode, logger):
regInd = opcode & 7
logger.info(regInd)
value = cpu.A - cpu.regs[regInd]
"""Flags"""
cpu.flags[ZF] = Bits.isZero(value)
cpu.flags[CF] = Bits.carryFlag(value)
cpu.flags[NF] = True
cpu.flags[HF] = Bits.halfCarrySub(cpu.A, value)
cpu.flags[SF] = Bits.signFlag(value)
cpu.flags[PVF] = Bits.overflow(cpu.A, value)
logger.info("CP r")
def cp_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
old = cpu.A
new = old - n
cpu.SFlag = Bits.isNegative(new)
cpu.ZFlag = Bits.isZero(new)
cpu.HFlag = Bits.halfCarrySub(old, new)
cpu.PVFlag = Bits.overflow(old, new)
cpu.NFlag = Bits.set()
cpu.CFlag = Bits.carryFlag(new)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("CP {:02X}".format(n))
def sbc_hl(cpu, opcode, logger):
old_val = cpu.A
cpu.A = old_val - cpu.ram[cpu.HL] - (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.NFlag = Bits.set()
cpu.HFlag = Bits.halfCarrySub(old_val, cpu.A)
cpu.PVFlag = Bits.overflow(old_val, cpu.A)
cpu.CFlag = Bits.carryFlag(cpu.A)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("SDC A, (HL)")
def or_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
old = cpu.A
cpu.A = cpu.A | n
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.HFlag = Bits.reset()
cpu.PVFlag = Bits.overflow(old, cpu.A)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("OR {:02X}".format(n))
def add_r(cpu, opcode, logger):
index = (opcode & 7)
old = cpu.A
cpu.A = old + cpu.regs[index]
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.HFlag = Bits.halfCarrySub(old, cpu.A)
cpu.PVFlag = Bits.overflow(old, cpu.A)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.carryFlag(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("ADD A, {}".format(IndexToReg.translate8Bit(index)))
def adc_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
old_val = cpu.A
new_val = cpu.A + n + (1 if cpu.CFlag else 0)
cpu.A = new_val
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.HFlag = Bits.halfCarrySub(old_val, cpu.A)
cpu.PVFlag = Bits.overflow(old_val, cpu.A)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.carryFlag(new_val)
logger.info("ADC A, {:02X}".format(n))
def add_iy(cpu, opcode, logger):
d = cpu.ram[cpu.PC]
value = cpu.A + cpu.ram[cpu.IY+d]
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.CFlag = Bits.carryFlag(value)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.overflow(cpu.A, value)
cpu.HFlag = Bits.halfCarrySub(cpu.A, value)
cpu.A = value
cpu.m_cycles, cpu.t_states = 4, 15
logger.info("ADD A, (IY+{:02X})".format(d))
def add_a_hl(cpu, opcode, logger):
oldA = cpu.A
value = cpu.A + cpu.ram[cpu.HL]
cpu.A = value
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.carryFlag(value)
cpu.PVFlag = Bits.overflow(oldA, cpu.A)
cpu.HFlag = Bits.halfCarrySub(cpu.A, oldA)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("ADD A, (HL)")
def adc_a_hl(cpu, opcode, logger):
v = cpu.ram[cpu.HL]
old = cpu.A
cpu.A += v
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.NFlag = Bits.reset()
cpu.PVFlag = Bits.overflow(old, cpu.A)
cpu.HFlag = Bits.halfCarrySub(cpu.A, old)
cpu.CFlag = Bits.carryFlag(old + v)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("ADC A, (HL)")
def sbc_r(cpu, opcode, logger):
reg_idx = (opcode & 7)
old_val = cpu.A
cpu.A = old_val - cpu.regs[reg_idx] - (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.NFlag = Bits.set()
cpu.HFlag = Bits.halfCarrySub(old_val, cpu.A)
cpu.PVFlag = Bits.overflow(old_val, cpu.A)
cpu.CFlag = Bits.carryFlag(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("SDC A, {}".format(IndexToReg.translate8Bit(reg_idx)))
def sub_a_hl(cpu, opcode, logger):
v = cpu.ram[cpu.HL]
old_A = cpu.AFPrim
cpu.A -= v
cpu.NFlag = Bits.set()
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.HFlag = Bits.halfCarrySub(old_A, cpu.A)
cpu.PVFlag = Bits.overflow(old_A, cpu.A)
cpu.CFlag = Bits.carryFlag(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 7
logger.info("SUB A, (HL)")
def sub_r(cpu, opcode, logger):
index = opcode & 7
old_A = cpu.A
cpu.A = cpu.A - cpu.regs[index]
cpu.NFlag = Bits.set()
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.HFlag = Bits.halfCarrySub(old_A, cpu.A)
cpu.PVFlag = Bits.overflow(cpu.A, old_A)
cpu.CFlag = Bits.carryFlag(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("SUB {}".format(IndexToReg.translate8Bit(index)))
def add_Hl_rr_c(cpu, opcode, logger):
regInd = (opcode >> 4) & 3
val = cpu.Reg16(regInd)
old = cpu.HL
cpu.HL = cpu.HL + val + (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.signFlag(cpu.HL, bits=16)
cpu.ZFlag = Bits.isZero(cpu.HL)
cpu.HFlag = Bits.halfCarrySub16(old, cpu.HL)
cpu.PVFlag = Bits.overflow(old, cpu.HL, bits=16)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.set() if (Bits.getNthBit(old, 15) == 1 and
Bits.getNthBit(cpu.HL, 15) == 0) else Bits.reset()
cpu.m_cycles, cpu.t_states = 4, 15
logger.info("ADC HL, {}".format(IndexToReg.translate16Bit(regInd)))
def add_r_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
old = cpu.A
value = cpu.A + n
cpu.A = value
cpu.SFlag = Bits.isNegative(value)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.HFlag = Bits.halfCarrySub(old, cpu.A)
cpu.PVFlag = Bits.overflow(old, cpu.A)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.carryFlag(value)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("ADD A, {:02X}".format(n))
def sbc(cpu, opcode, logger):
regInd = (opcode & 0x30) >> 4
value = cpu.Reg16(regInd)
oldHL = cpu.HL
cpu.HL = cpu.HL - value - (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.signFlag(cpu.HL, bits=16)
cpu.ZFlag = Bits.isZero(cpu.HL)
cpu.HFlag = Bits.halfCarrySub16(oldHL, cpu.HL)
cpu.PVFlag = Bits.overflow(oldHL, cpu.HL, bits=16)
cpu.NFlag = Bits.set()
cpu.CFlag = Bits.borrow(cpu.HL, bits=16)
cpu.m_cycles, cpu.t_states = 4, 15
logger.info("SBC HL, {}".format(IndexToReg.translate16Bit(regInd)))
