def neg(cpu, opcode, logger):
old = cpu.A
cpu.A = 0 - cpu.A
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.set() if old == 0x80 else Bits.reset()
cpu.CFlag = Bits.isZero(old)
cpu.HFlag = Bits.halfCarrySub(0x0, old)
cpu.m_cycles, cpu.t_states = 2, 8
logger.info("NEG")
def sbc(cpu, opcode, logger):
logger.info("SBC HL")
regInd = (opcode & 0x30) >> 4
value = 0
if regInd == 0:
value = cpu.BC
elif regInd == 1:
value = cpu.DE
elif regInd == 2:
value = cpu.HL
elif regInd == 3:
value = cpu.SP
oldHL = cpu.HL
logger.info("Old value of HL: " + str(oldHL))
cpu.HL = cpu.HL - value - (1 if cpu.CFlag else 0)
logger.info("New value of HL: " + str(cpu.HL))
cpu.flags[SF] = Bits.signFlag(cpu.HL, bits=16)
cpu.flags[ZF] = Bits.isZero(cpu.HL)
cpu.flags[HF] = Bits.halfCarrySub16(oldHL, cpu.HL)
cpu.flags[PVF] = Bits.overflow(Bits.twos_comp(oldHL, bits=16),
Bits.twos_comp(cpu.HL, bits=16))
cpu.flags[NF] = True
cpu.flags[CF] = Bits.borrow(cpu.HL, bits=16)
def _and(cpu, opcode, logger):
logger.info("AND A")
regInd = opcode & 7
cpu.A = cpu.A & cpu.regs[regInd]
cpu.flags[HF] = True
cpu.flags[CF] = False
cpu.flags[NF] = False
cpu.flags[ZF] = Bits.isZero(cpu.A)
cpu.flags[SF] = Bits.signInTwosComp(cpu.A)
cpu.flags[PVF] = Bits.paritySet(cpu.A)
def dec_at_hl(cpu, opcode, logger):
old_val = cpu.ram[cpu.HL]
new_val = old_val - 1
cpu.ram[cpu.HL] = new_val
cpu.ZFlag = Bits.isZero(new_val)
cpu.SFlag = Bits.isNegative(new_val)
cpu.NFlag = Bits.set()
cpu.PVFlag = Bits.halfCarrySub(old_val, new_val)
cpu.m_cycles, cpu.t_states = 3, 11
logger.info("DEC (HL)")
def cp(cpu, opcode, logger):
regInd = opcode & 7
value = cpu.A - cpu.regs[regInd]
cpu.ZFlag = Bits.isZero(value)
cpu.CFlag = Bits.carryFlag(value)
cpu.NFlag = Bits.set()
cpu.HFlag = Bits.halfCarrySub(cpu.A, value)
cpu.SFlag = Bits.signFlag(value)
cpu.PVFlag = Bits.overflow(value, cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("CP {}".format(IndexToReg.translate8Bit(regInd)))
def inc8(cpu, opcode, logger):
logger.info("INC r")
index = ( opcode >> 3 ) & 7
oldValue = cpu.regs[index]
cpu.regs[index] = (cpu.regs[index] + 1 ) & 0xFF
cpu.NFlag = False
cpu.ZFlag = Bits.isZero(cpu.regs[index])
cpu.HFlag = Bits.halfCarrySub(oldValue, cpu.regs[index])
cpu.PVFlag = True if oldValue == 0x7f else False
cpu.SFlag = Bits.twos_comp(cpu.regs[index]) < 0
def adc_r(cpu, opcode, logger):
reg_idx = (opcode & 7)
old_val = cpu.A
cpu.A = old_val + cpu.regs[reg_idx] + (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.NFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("ADC A, {}".format(IndexToReg.translate8Bit(reg_idx)))
def ldar(cpu, opcode, logger):
cpu.A = cpu.R
cpu.SFlag = Bits.isNegative(cpu.R)
cpu.ZFlag = Bits.isZero(cpu.R)
cpu.HFlag = Bits.reset()
cpu.PVFlag = Bits.set() if cpu.iff2 == 1 else Bits.reset()
cpu.NFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 2, 9
logger.info("LD A, R")
def dec_at_ix_d(cpu, opcode, logger):
d = cpu.ram[cpu.PC]
old_val = cpu.ram[cpu.IX+d]
new_val = old_val - 1
cpu.ram[cpu.IX+d] = new_val
cpu.ZFlag = Bits.isZero(new_val)
cpu.SFlag = Bits.isNegative(new_val)
cpu.NFlag = Bits.set()
cpu.PVFlag = Bits.halfCarrySub(old_val, new_val)
cpu.m_cycles, cpu.t_states = 6, 23
logger.info("DEC (IX+{:02X})".format(d))
def xorA(cpu, opcode, logger):
regInd = opcode & 7
cpu.A = cpu.A ^ cpu.regs[regInd]
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.HFlag = Bits.reset()
cpu.SFlag = Bits.signInTwosComp(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("XOR A")
def _or_hl(cpu, opcode, logger):
cpu.A = cpu.A | cpu.ram[cpu.HL]
cpu.HFlag = Bits.reset()
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("OR (HL)")
def cp_hl(cpu, opcode, logger):
value = cpu.A - cpu.ram[cpu.HL]
cpu.ZFlag = Bits.isZero(value)
cpu.CFlag = Bits.carryFlag(value)
cpu.NFlag = Bits.set()
cpu.HFlag = Bits.halfCarrySub(cpu.A, value)
cpu.SFlag = Bits.signFlag(value)
cpu.PVFlag = Bits.overflow(value, cpu.A)
cpu.m_cycles, cpu.t_states = 1, 7
logger.info("CP (HL)")
def xorA(cpu, opcode, logger):
"""XOR A"""
regInd = opcode & 7
cpu.A = cpu.A ^ cpu.regs[regInd]
"""Flags"""
cpu.flags[ZF] = Bits.isZero(cpu.A)
cpu.flags[CF] = False
cpu.flags[NF] = False
cpu.flags[HF] = False
cpu.flags[SF] = Bits.signInTwosComp(cpu.A)
cpu.flags[PVF] = Bits.paritySet(cpu.A)
logger.info("XOR A")
def sub_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
value = cpu.A - n
cpu.NFlag = Bits.set()
cpu.ZFlag = Bits.isZero(value)
cpu.HFlag = Bits.halfCarrySub(cpu.A, value)
cpu.PVFlag = Bits.overflow(cpu.A, value)
cpu.CFlag = Bits.carryFlag(value)
cpu.A = value
logger.info("SUB {:02X}".format(n))
def _or(cpu, opcode, logger):
regInd = opcode & 7
cpu.A = cpu.A | cpu.regs[regInd]
cpu.HFlag = Bits.reset()
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("OR {}".format(IndexToReg.translate8Bit(regInd)))
def cp(cpu, opcode, logger):
regInd = opcode & 7
logger.info(regInd)
value = cpu.A - cpu.regs[regInd]
"""Flags"""
cpu.flags[ZF] = Bits.isZero(value)
cpu.flags[CF] = Bits.carryFlag(value)
cpu.flags[NF] = True
cpu.flags[HF] = Bits.halfCarrySub(cpu.A, value)
cpu.flags[SF] = Bits.signFlag(value)
cpu.flags[PVF] = Bits.overflow(cpu.A, value)
logger.info("CP r")
def dec8b(cpu, opcode, logger):
reg_index = (opcode >> 3) & 7
old_val = cpu.regs[reg_index]
cpu.regs[reg_index] = cpu.regs[reg_index] - 1
cpu.ZFlag = Bits.isZero(cpu.regs[reg_index])
cpu.SFlag = Bits.isNegative(cpu.regs[reg_index])
cpu.NFlag = Bits.set()
cpu.PVFlag = Bits.halfCarrySub(old_val, cpu.regs[reg_index])
cpu.HFlag = Bits.halfCarrySub(old_val, cpu.regs[reg_index])
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("DEC {}".format(IndexToReg.translate8Bit(reg_index)))
def _and_hl(cpu, opcode, logger):
val = cpu.ram[cpu.HL]
cpu.A = cpu.A & val
cpu.HFlag = Bits.set()
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.signInTwosComp(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 7
logger.info("AND (HL)")
def sbc_hl(cpu, opcode, logger):
old_val = cpu.A
cpu.A = old_val - cpu.ram[cpu.HL] - (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.NFlag = Bits.set()
cpu.HFlag = Bits.halfCarrySub(old_val, cpu.A)
cpu.PVFlag = Bits.overflow(old_val, cpu.A)
cpu.CFlag = Bits.carryFlag(cpu.A)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("SDC A, (HL)")
def cp_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
old = cpu.A
new = old - n
cpu.SFlag = Bits.isNegative(new)
cpu.ZFlag = Bits.isZero(new)
cpu.HFlag = Bits.halfCarrySub(old, new)
cpu.PVFlag = Bits.overflow(old, new)
cpu.NFlag = Bits.set()
cpu.CFlag = Bits.carryFlag(new)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("CP {:02X}".format(n))
def dec_mem_at_iy(cpu, opcode, logger):
displacement = cpu.ram[cpu.PC]
addr = cpu.IY + displacement
value = cpu.ram[addr]
new_value = value - 1
cpu.ram[addr] = new_value
cpu.NFlag = Bits.set()
cpu.SFlag = Bits.isNegative(new_value)
cpu.ZFlag = Bits.isZero(new_value)
cpu.PVFlag = True if value == 0x80 else False
cpu.HFlag = Bits.halfCarrySub(value, new_value)
logger.info("DEC (IY+{:2X})".format(displacement))
def inc8(cpu, opcode, logger):
index = (opcode >> 3) & 7
oldValue = cpu.regs[index]
cpu.regs[index] = Bits.limitTo8Bits(cpu.regs[index] + 1)
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.regs[index])
cpu.HFlag = Bits.halfCarrySub(oldValue, cpu.regs[index])
cpu.PVFlag = True if oldValue == 0x7f else False
cpu.SFlag = Bits.isNegative(cpu.regs[index])
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("INC {}".format(IndexToReg.translate8Bit(index)))
def adc_a_hl(cpu, opcode, logger):
v = cpu.ram[cpu.HL]
old = cpu.A
cpu.A += v
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.NFlag = Bits.reset()
cpu.PVFlag = Bits.overflow(old, cpu.A)
cpu.HFlag = Bits.halfCarrySub(cpu.A, old)
cpu.CFlag = Bits.carryFlag(old + v)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("ADC A, (HL)")
def sub_a_hl(cpu, opcode, logger):
v = cpu.ram[cpu.HL]
old_A = cpu.AFPrim
cpu.A -= v
cpu.NFlag = Bits.set()
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.HFlag = Bits.halfCarrySub(old_A, cpu.A)
cpu.PVFlag = Bits.overflow(old_A, cpu.A)
cpu.CFlag = Bits.carryFlag(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 7
logger.info("SUB A, (HL)")
def add_r(cpu, opcode, logger):
index = (opcode & 7)
old = cpu.A
cpu.A = old + cpu.regs[index]
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.HFlag = Bits.halfCarrySub(old, cpu.A)
cpu.PVFlag = Bits.overflow(old, cpu.A)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.carryFlag(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("ADD A, {}".format(IndexToReg.translate8Bit(index)))
def or_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
old = cpu.A
cpu.A = cpu.A | n
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.HFlag = Bits.reset()
cpu.PVFlag = Bits.overflow(old, cpu.A)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("OR {:02X}".format(n))
def sbc_r(cpu, opcode, logger):
reg_idx = (opcode & 7)
old_val = cpu.A
cpu.A = old_val - cpu.regs[reg_idx] - (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.NFlag = Bits.set()
cpu.HFlag = Bits.halfCarrySub(old_val, cpu.A)
cpu.PVFlag = Bits.overflow(old_val, cpu.A)
cpu.CFlag = Bits.carryFlag(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("SDC A, {}".format(IndexToReg.translate8Bit(reg_idx)))
def add_iy(cpu, opcode, logger):
d = cpu.ram[cpu.PC]
value = cpu.A + cpu.ram[cpu.IY+d]
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.CFlag = Bits.carryFlag(value)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.overflow(cpu.A, value)
cpu.HFlag = Bits.halfCarrySub(cpu.A, value)
cpu.A = value
cpu.m_cycles, cpu.t_states = 4, 15
logger.info("ADD A, (IY+{:02X})".format(d))
def xor_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
old = cpu.A
cpu.A = old ^ n
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.HFlag = Bits.reset()
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("XOR {:02X}".format(n))
def adc_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
old_val = cpu.A
new_val = cpu.A + n + (1 if cpu.CFlag else 0)
cpu.A = new_val
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.HFlag = Bits.halfCarrySub(old_val, cpu.A)
cpu.PVFlag = Bits.overflow(old_val, cpu.A)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.carryFlag(new_val)
logger.info("ADC A, {:02X}".format(n))
def test_bits_isZero_returns_true_when_value_is_zero(self):
self.assertTrue(Bits.isZero(0))
def test_bits_isZero_returns_false_when_value_is_non_zero(self):
self.assertFalse(Bits.isZero(1))
