def _handle_index_extension(s, node, value, idx, dscp, inclusive=True):
expected_nbits = value.Type.get_index_width()
idx_nbits = idx.Type.get_dtype().get_length()
is_idx_reinterpretable = not idx._is_explicit
if not inclusive and hasattr(idx, '_value'):
idx_nbits = s._get_nbits_from_value(idx._value - 1)
if idx_nbits > expected_nbits:
# Either bitwidth do not match or requires implicit truncation
raise PyMTLTypeError(
s.blk, node.ast,
f'expects a {expected_nbits}-bit index but the given {dscp} has more ({idx_nbits}) bits!'
)
elif idx_nbits < expected_nbits:
if is_idx_reinterpretable:
# Implicit zero-extension
s.enforcer.enter(s.blk, rt.NetWire(rdt.Vector(expected_nbits)),
idx)
else:
# Bitwidth mismatch
raise PyMTLTypeError(
s.blk, node.ast,
f'expects a {expected_nbits}-bit index but the given {dscp} has {idx_nbits} bits!'
)
else:
if idx_nbits != idx.Type.get_dtype().get_length():
# If we used a different bitwidth then enforce it
s.enforcer.enter(s.blk, rt.NetWire(rdt.Vector(idx_nbits)), idx)
def visit_Slice( s, node ):
lower_val = None if not hasattr(node.lower, "_value") else node.lower._value
upper_val = None if not hasattr(node.upper, "_value") else node.upper._value
dtype = node.value.Type.get_dtype()
if not isinstance( dtype, rdt.Vector ):
raise PyMTLTypeError( s.blk, node.ast, f'cannot perform slicing on type {dtype}!')
if not lower_val is None and not upper_val is None:
signal_nbits = dtype.get_length()
# upper bound must be strictly larger than the lower bound
if ( lower_val >= upper_val ):
raise PyMTLTypeError( s.blk, node.ast,
'the upper bound of a slice must be larger than the lower bound!' )
# upper & lower bound should be less than the bit width of the signal
if not ( 0 <= lower_val < upper_val <= signal_nbits ):
raise PyMTLTypeError( s.blk, node.ast,
'upper/lower bound of slice out of width of signal!' )
node.Type = rt.NetWire( rdt.Vector( int( upper_val - lower_val ) ) )
else:
# Try to special case the constant-stride part selection
try:
assert isinstance( node.upper, bir.BinOp )
assert isinstance( node.upper.op, bir.Add )
nbits = node.upper.right
slice_size = nbits._value
assert s.is_same( node.lower, node.upper.left )
node.Type = rt.NetWire( rdt.Vector( slice_size ) )
# Add new fields that might help translation
node.size = slice_size
node.base = node.lower
except Exception:
raise PyMTLTypeError( s.blk, node.ast, 'slice bounds must be constant!' )
def visit_Compare( s, node ):
l_type = node.left.Type.get_dtype()
r_type = node.right.Type.get_dtype()
l_explicit, r_explicit = node.left._is_explicit, node.right._is_explicit
l_nbits, r_nbits = l_type.get_length(), r_type.get_length()
if l_explicit and r_explicit:
if l_type != r_type:
raise PyMTLTypeError( s.blk, node.ast,
f"LHS and RHS of {node.op.__class__.__name__} have different types ({l_type} vs {r_type})!" )
elif not l_explicit and not r_explicit:
if l_nbits >= r_nbits:
target_nbits = l_nbits
op = node.right
else:
target_nbits = r_nbits
op = node.left
context = rt.NetWire(rdt.Vector(target_nbits))
s.enforcer.enter( s.blk, context, op )
else:
context, op, explicit, implicit = node.left.Type, node.right, l_nbits, r_nbits
if not l_explicit:
context, op, explicit, implicit = node.right.Type, node.left, r_nbits, l_nbits
# Check if any implicit truncation happens
if explicit < implicit:
raise PyMTLTypeError( s.blk, node.ast,
f"The explicitly sized side of comparison has {explicit} bits but "
f"the integer literal requires more bits ({implicit}) to hold!" )
s.enforcer.enter( s.blk, context, op )
node.Type = rt.NetWire( rdt.Bool() )
node._is_explicit = True
def visit_Compare( s, node ):
l_type = node.left.Type.get_dtype()
r_type = node.right.Type.get_dtype()
if l_type != r_type:
raise PyMTLTypeError( s.blk, node.ast,
f"LHS and RHS of {node.op.__class__.__name__} have different types ({l_type} vs {r_type})!" )
node.Type = rt.NetWire( rdt.Bool() )
def visit_UnaryOp( s, node ):
if isinstance( node.op, bir.Not ):
dtype = node.operand.Type.get_dtype()
if not rdt.Bool()( dtype ):
raise PyMTLTypeError( s.blk, node.ast,
'the operand of "Logic-not" cannot be cast to bool!' )
if dtype.get_length() != 1:
raise PyMTLTypeError( s.blk, node.ast,
'the operand of "Logic-not" is not a single bit!' )
node.Type = rt.NetWire( rdt.Bool() )
else:
node.Type = node.operand.Type
if hasattr( node.operand, '_value' ):
opmap = {
bir.Invert : '~',
bir.Not : 'not',
bir.UAdd : '+',
bir.USub : '-',
}
try:
op = opmap[node.op.__class__]
operand = node.operand._value.uint()
node._value = eval(f"Bits32({op}{operand})")
except:
pass
def visit_Index(s, node):
idx = None if not hasattr(node.idx, "_value") else node.idx._value
if isinstance(node.value.Type, rt.Array):
if idx is not None and not (0 <= idx <
node.value.Type.get_dim_sizes()[0]):
raise PyMTLTypeError(s.blk, node.ast,
'array index out of range!')
node.Type = node.value.Type.get_next_dim_type()
obj = node.value.Type.get_obj()
if idx is not None and obj is not None:
if isinstance(node.Type, rt.Array):
node.Type.obj = obj[int(idx)]
else:
node._value = obj[int(idx)]
elif isinstance(node.value.Type, rt.Signal):
dtype = node.value.Type.get_dtype()
if node.value.Type.is_packed_indexable():
if idx is not None and not (0 <= idx < dtype.get_length()):
raise PyMTLTypeError(s.blk, node.ast,
'bit selection index out of range!')
node.Type = node.value.Type.get_next_dim_type()
elif isinstance(dtype, rdt.Vector):
if idx is not None and not (0 <= idx < dtype.get_length()):
raise PyMTLTypeError(s.blk, node.ast,
'bit selection index out of range!')
node.Type = rt.NetWire(rdt.Vector(1))
else:
raise PyMTLTypeError(s.blk, node.ast,
f'cannot perform index on {dtype}!')
else:
# Should be unreachable
raise PyMTLTypeError(
s.blk, node.ast, f'cannot perform index on {node.value.Type}!')
def visit_IfExp(s, node):
# Can the type of condition be cast into bool?
if not rdt.Bool()(node.cond.Type.get_dtype()):
raise PyMTLTypeError(
s.blk, node.ast,
'the condition of "if-exp" cannot be converted to bool!')
# body and orelse must have the same type
# if node.body.Type != node.orelse.Type:
if not node.body.Type.get_dtype()(node.orelse.Type.get_dtype()):
raise PyMTLTypeError(
s.blk, node.ast,
'the body and orelse of "if-exp" must have the same type!')
lhs_dtype, rhs_dtype = node.body.Type.get_dtype(
), node.orelse.Type.get_dtype()
lhs_is_vector = isinstance(lhs_dtype, rdt.Vector)
rhs_is_vector = isinstance(rhs_dtype, rdt.Vector)
lhs_nbits, rhs_nbits = lhs_dtype.get_length(), rhs_dtype.get_length()
# Unify body and orelse if both are rdt.Vector
if lhs_is_vector and rhs_is_vector and lhs_nbits != rhs_nbits:
is_lhs_inferred = not node.body._is_explicit
is_rhs_inferred = not node.orelse._is_explicit
# Both sides are explicit
if not is_lhs_inferred and not is_rhs_inferred:
raise PyMTLTypeError(
s.blk, node.ast,
f'the body and orelse of "if-exp" have different bitwidth {lhs_nbits} vs {rhs_nbits}!'
)
# Both sides are implicit
elif is_lhs_inferred and is_rhs_inferred:
if lhs_nbits >= rhs_nbits:
target_nbits = lhs_nbits
op = node.body
else:
target_nbits = rhs_nbits
op = node.orelse
context = rt.NetWire(rdt.Vector(target_nbits))
s.enforcer.enter(s.blk, context, op)
else:
# One side is explicit and the other implicit
if is_lhs_inferred:
exp_str, imp_str = "or-else", "body"
context, op, explicit, implicit = node.orelse.Type, node.body, rhs_nbits, lhs_nbits
else:
exp_str, imp_str = "body", "or-else"
context, op, explicit, implicit = node.body.Type, node.orelse, lhs_nbits, rhs_nbits
if explicit < implicit:
raise PyMTLTypeError(
s.blk, node.ast,
f"The {exp_str} side of if-exp has {explicit} bits but "
f"the {imp_str} side requires more bits ({implicit})!")
s.enforcer.enter(s.blk, context, op)
node.Type = node.body.Type
node._is_explicit = node.body._is_explicit or node.orelse._is_explicit
def visit_BoolOp(s, node):
for value in node.values:
if not isinstance(value.Type, rt.Signal) or not rdt.Bool()(
value.Type.get_dtype()):
raise PyMTLTypeError(
s.blk, node.ast,
f"{value} of {value.Type} cannot be cast into bool!")
node.Type = rt.NetWire(rdt.Bool())
def visit_Concat(s, node):
nbits = 0
for child in node.values:
if not isinstance(child.Type, rt.Signal):
raise PyMTLTypeError(s.blk, node.ast,
f'{child} is not a signal!')
nbits += child.Type.get_dtype().get_length()
node.Type = rt.NetWire(rdt.Vector(nbits))
def visit_UnaryOp( s, node ):
if isinstance( node.op, bir.Not ):
dtype = node.operand.Type.get_dtype()
if not rdt.Bool()( dtype ):
raise PyMTLTypeError( s.blk, node.ast,
'the operand of "Logic-not" cannot be cast to bool!' )
if dtype.get_length() != 1:
raise PyMTLTypeError( s.blk, node.ast,
'the operand of "Logic-not" is not a single bit!' )
node.Type = rt.NetWire( rdt.Bool() )
else:
node.Type = node.operand.Type
def visit_Slice(s, node):
lower_val = getattr(node.lower, '_value', None)
upper_val = getattr(node.upper, '_value', None)
dtype = node.value.Type.get_dtype()
if not isinstance(dtype, rdt.Vector):
raise PyMTLTypeError(
s.blk, node.ast,
'cannot perform slicing on type {}!'.format(dtype))
if not lower_val is None and not upper_val is None:
signal_nbits = dtype.get_length()
# upper bound must be strictly larger than the lower bound
if (lower_val >= upper_val):
raise PyMTLTypeError(
s.blk, node.ast,
'the upper bound of a slice must be larger than the lower bound!'
)
# upper & lower bound should be less than the bit width of the signal
if not (0 <= lower_val < upper_val <= signal_nbits):
raise PyMTLTypeError(
s.blk, node.ast,
'upper/lower bound of slice out of width of signal!')
node.Type = rt.NetWire(rdt.Vector(int(upper_val - lower_val)))
else:
# Try to special case the constant-stride part selection
try:
assert isinstance(node.upper, bir.BinOp)
assert isinstance(node.upper.op, bir.Add)
nbits = node.upper.right
assert s.is_same(node.lower, node.upper.left)
node.Type = rt.NetWire(rdt.Vector(nbits))
except Exception:
raise PyMTLTypeError(s.blk, node.ast,
'slice bounds must be constant!')
def visit_Index(s, node):
idx = None if not hasattr(node.idx, "_value") else int(node.idx._value)
if isinstance(node.value.Type, rt.Array):
if idx is not None and not (0 <= idx <
node.value.Type.get_dim_sizes()[0]):
raise PyMTLTypeError(s.blk, node.ast,
'array index out of range!')
node.Type = node.value.Type.get_next_dim_type()
obj = node.value.Type.get_obj()
s._handle_index_extension(node, node.value, node.idx, 'index')
# If the given index yields an integer, mark this node as implicit
if idx is not None and obj is not None:
if isinstance(node.Type, rt.Array):
node.Type.obj = obj[int(idx)]
node._is_explicit = True
else:
node._value = int(obj[int(idx)])
node._is_explicit = False if isinstance(node._value,
int) else True
else:
node._is_explicit = True
elif isinstance(node.value.Type, rt.Signal):
dtype = node.value.Type.get_dtype()
s._handle_index_extension(node, node.value, node.idx, 'index')
if node.value.Type.is_packed_indexable():
if idx is not None and not (0 <= idx < dtype.get_length()):
raise PyMTLTypeError(s.blk, node.ast,
'bit selection index out of range!')
node.Type = node.value.Type.get_next_dim_type()
node._is_explicit = True
elif isinstance(dtype, rdt.Vector):
if idx is not None and not (0 <= idx < dtype.get_length()):
raise PyMTLTypeError(s.blk, node.ast,
'bit selection index out of range!')
node.Type = rt.NetWire(rdt.Vector(1))
node._is_explicit = True
else:
raise PyMTLTypeError(s.blk, node.ast,
f'cannot perform index on {dtype}!')
else:
# Should be unreachable
raise PyMTLTypeError(
s.blk, node.ast, f'cannot perform index on {node.value.Type}!')
def visit_BinOp(s, node):
op = node.op
l_type = node.left.Type.get_dtype()
r_type = node.right.Type.get_dtype()
if not (rdt.Vector(1)(l_type) and rdt.Vector(1)(r_type)):
raise PyMTLTypeError(
s.blk, node.ast,
f"both sides of {op.__class__.__name__} should be of vector type!"
)
if not isinstance(op, s.BinOp_left_nbits) and l_type != r_type:
raise PyMTLTypeError(
s.blk, node.ast,
f"LHS and RHS of {op.__class__.__name__} should have the same type ({l_type} vs {r_type})!"
)
l_nbits = l_type.get_length()
r_nbits = r_type.get_length()
# Enforcing Verilog bitwidth inference rules
res_nbits = 0
if isinstance(op, s.BinOp_max_nbits):
res_nbits = max(l_nbits, r_nbits)
elif isinstance(op, s.BinOp_left_nbits):
res_nbits = l_nbits
else:
raise Exception('RTLIRTypeCheck internal error: unrecognized op!')
try:
# Both sides are constant expressions
l_val = node.left._value
r_val = node.rigth._value
node._value = s.eval_const_binop(l_val, op, r_val)
node.Type = rt.Const(rdt.Vector(res_nbits))
except AttributeError:
# Both sides are constant but the value cannot be determined statically
if isinstance(node.left.Type, rt.Const) and isinstance(
node.right.Type, rt.Const):
node.Type = rt.Const(rdt.Vector(res_nbits), None)
# Variable
else:
node.Type = rt.NetWire(rdt.Vector(res_nbits))
def visit_BinOp(s, node):
op = node.op
l_type = node.left.Type.get_dtype()
r_type = node.right.Type.get_dtype()
l_explicit, r_explicit = node.left._is_explicit, node.right._is_explicit
if not (rdt.Vector(1)(l_type) and rdt.Vector(1)(r_type)):
raise PyMTLTypeError(
s.blk, node.ast,
f"both sides of {op.__class__.__name__} should be of vector type!"
)
l_nbits = l_type.get_length()
r_nbits = r_type.get_length()
# Enforcing Verilog bitwidth inference rules
res_nbits = 0
if isinstance(op, s.BinOp_max_nbits):
if (not l_explicit and r_explicit) or (l_explicit
and not r_explicit):
context, op, explicit, implicit = node.left.Type, node.right, l_nbits, r_nbits
if not l_explicit:
context, op, explicit, implicit = node.right.Type, node.left, r_nbits, l_nbits
# Check if any implicit truncation happens
if explicit < implicit:
raise PyMTLTypeError(
s.blk, node.ast,
f"The explicitly sized side of operation has {explicit} bits but "
f"the integer literal requires more bits ({implicit})!"
)
s.enforcer.enter(s.blk, context, op)
elif not l_explicit and not r_explicit:
# Both sides are implicit
if l_nbits >= r_nbits:
target_nbits = l_nbits
op = node.right
else:
target_nbits = r_nbits
op = node.left
context = rt.NetWire(rdt.Vector(target_nbits))
s.enforcer.enter(s.blk, context, op)
else:
# Both sides are explicit
if not isinstance(op, s.BinOp_left_nbits) and l_type != r_type:
raise PyMTLTypeError(
s.blk, node.ast,
f"LHS and RHS of {op.__class__.__name__} should have the same type ({l_type} vs {r_type})!"
)
res_nbits = max(l_nbits, r_nbits)
node._is_explicit = l_explicit or r_explicit
elif isinstance(op, s.BinOp_left_nbits):
res_nbits = l_nbits
node._is_explicit = l_explicit
else:
raise Exception('RTLIRTypeCheck internal error: unrecognized op!')
try:
# Both sides are constant expressions
l_val = node.left._value
r_val = node.right._value
node._value = s.eval_const_binop(l_val, node.op, r_val)
node.Type = s.rtlir_getter.get_rtlir(node._value)
assert isinstance(node.Type, rt.Const)
except AttributeError:
# Both sides are constant but the value cannot be determined statically
if isinstance(node.left.Type, rt.Const) and isinstance(
node.right.Type, rt.Const):
node.Type = rt.Const(rdt.Vector(res_nbits), None)
# Variable
else:
node.Type = rt.NetWire(rdt.Vector(res_nbits))
