def test_pymtl3_list_interface_views():
a = CaseBits32MsgRdyIfcOnly.DUT()
a.elaborate()
assert rt.is_rtlir_convertible(a.in_)
assert rt.get_rtlir( a.in_ ) == \
rt.Array([5], rt.InterfaceView('Bits32MsgRdyIfc',
{'msg':rt.Port('output', rdt.Vector(32)), 'rdy':rt.Port('input', rdt.Vector(1))}))
def test_pymtl3_list_consts():
class A(dsl.Component):
def construct(s):
s.in_ = [Bits32(42) for _ in range(5)]
a = A()
a.elaborate()
assert rt.is_rtlir_convertible(a.in_)
assert rt.Array([5], rt.Const(rdt.Vector(32))) == rt.get_rtlir(a.in_)
def test_pymtl_list_components():
a = CaseBits32InOutx5CompOnly.DUT()
a.elaborate()
assert rt.is_rtlir_convertible(a.b)
assert rt.get_rtlir( a.b ) == \
rt.Array([5], rt.Component( a.b[0], {
'clk':rt.Port('input', rdt.Vector(1)),
'reset':rt.Port('input', rdt.Vector(1)),
'in_':rt.Port('input', rdt.Vector(32)),
'out':rt.Port('output', rdt.Vector(32)),
}))
def test_pymtl_list_multi_dimension():
class A(dsl.Component):
def construct(s):
s.out = [[[dsl.OutPort(Bits32) for _ in range(1)] \
for _ in range(2)] for _ in range(3)]
a = A()
a.elaborate()
assert rt.is_rtlir_convertible(a.out)
assert rt.Array([3, 2, 1], rt.Port('output',
rdt.Vector(32))) == rt.get_rtlir(a.out)
def test_pymtl_list_components():
class B(dsl.Component):
def construct(s):
s.in_ = dsl.InPort(Bits32)
s.out = dsl.OutPort(Bits32)
class A(dsl.Component):
def construct(s):
s.b = [B() for _ in range(5)]
a = A()
a.elaborate()
assert rt.is_rtlir_convertible(a.b)
assert rt.Array([5], rt.Component( a.b[0],
{'in_':rt.Port('input', rdt.Vector(32)), 'out':rt.Port('output', rdt.Vector(32))})) == \
rt.get_rtlir( a.b )
def test_pymtl3_list_interface_views():
class Ifc(dsl.Interface):
def construct(s):
s.msg = dsl.OutPort(Bits32)
s.rdy = dsl.InPort(Bits1)
class A(dsl.Component):
def construct(s):
s.in_ = [Ifc() for _ in range(5)]
a = A()
a.elaborate()
assert rt.is_rtlir_convertible(a.in_)
assert rt.Array([5],
rt.InterfaceView('Ifc',
{'msg':rt.Port('output', rdt.Vector(32)), 'rdy':rt.Port('input', rdt.Vector(1))})) == \
rt.get_rtlir( a.in_ )
def test_pymtl_list_multi_dimension():
a = CaseBits32Outx3x2x1PortOnly.DUT()
a.elaborate()
assert rt.is_rtlir_convertible(a.out)
assert rt.get_rtlir(a.out) == rt.Array([3, 2, 1],
rt.Port('output', rdt.Vector(32)))
def test_pymtl3_list_consts():
a = CaseBits32x5ConstOnly.DUT()
a.elaborate()
assert rt.is_rtlir_convertible(a.in_)
assert rt.get_rtlir(a.in_) == rt.Array([5], rt.Const(rdt.Vector(32)))
def test_pymtl3_list_ports():
a = CaseBits32x5PortOnly.DUT()
a.elaborate()
assert rt.is_rtlir_convertible(a.in_)
assert rt.get_rtlir(a.in_) == rt.Array([5],
rt.Port('input', rdt.Vector(32)))
def test_pymtl3_list_wires(): a = CaseBits32x5WireOnly.DUT() a.elaborate() assert rt.is_rtlir_convertible( a.in_ ) assert rtlir_getter.get_rtlir( a.in_ ) == rt.Array([5], rt.Wire(rdt.Vector(32)))
