def sbc(cpu, opcode, logger):
logger.info("SBC HL")
regInd = (opcode & 0x30) >> 4
value = 0
if regInd == 0:
value = cpu.BC
elif regInd == 1:
value = cpu.DE
elif regInd == 2:
value = cpu.HL
elif regInd == 3:
value = cpu.SP
oldHL = cpu.HL
logger.info("Old value of HL: " + str(oldHL))
cpu.HL = cpu.HL - value - (1 if cpu.CFlag else 0)
logger.info("New value of HL: " + str(cpu.HL))
cpu.flags[SF] = Bits.signFlag(cpu.HL, bits=16)
cpu.flags[ZF] = Bits.isZero(cpu.HL)
cpu.flags[HF] = Bits.halfCarrySub16(oldHL, cpu.HL)
cpu.flags[PVF] = Bits.overflow(Bits.twos_comp(oldHL, bits=16),
Bits.twos_comp(cpu.HL, bits=16))
cpu.flags[NF] = True
cpu.flags[CF] = Bits.borrow(cpu.HL, bits=16)
def add_Hl_rr_c(cpu, opcode, logger):
regInd = (opcode >> 4) & 3
val = cpu.Reg16(regInd)
old = cpu.HL
cpu.HL = cpu.HL + val + (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.signFlag(cpu.HL, bits=16)
cpu.ZFlag = Bits.isZero(cpu.HL)
cpu.HFlag = Bits.halfCarrySub16(old, cpu.HL)
cpu.PVFlag = Bits.overflow(old, cpu.HL, bits=16)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.set() if (Bits.getNthBit(old, 15) == 1 and
Bits.getNthBit(cpu.HL, 15) == 0) else Bits.reset()
cpu.m_cycles, cpu.t_states = 4, 15
logger.info("ADC HL, {}".format(IndexToReg.translate16Bit(regInd)))
def sbc(cpu, opcode, logger):
regInd = (opcode & 0x30) >> 4
value = cpu.Reg16(regInd)
oldHL = cpu.HL
cpu.HL = cpu.HL - value - (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.signFlag(cpu.HL, bits=16)
cpu.ZFlag = Bits.isZero(cpu.HL)
cpu.HFlag = Bits.halfCarrySub16(oldHL, cpu.HL)
cpu.PVFlag = Bits.overflow(oldHL, cpu.HL, bits=16)
cpu.NFlag = Bits.set()
cpu.CFlag = Bits.borrow(cpu.HL, bits=16)
cpu.m_cycles, cpu.t_states = 4, 15
logger.info("SBC HL, {}".format(IndexToReg.translate16Bit(regInd)))
