def _and(cpu, opcode, logger):
logger.info("AND A")
regInd = opcode & 7
cpu.A = cpu.A & cpu.regs[regInd]
cpu.flags[HF] = True
cpu.flags[CF] = False
cpu.flags[NF] = False
cpu.flags[ZF] = Bits.isZero(cpu.A)
cpu.flags[SF] = Bits.signInTwosComp(cpu.A)
cpu.flags[PVF] = Bits.paritySet(cpu.A)
def xorA(cpu, opcode, logger):
regInd = opcode & 7
cpu.A = cpu.A ^ cpu.regs[regInd]
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.HFlag = Bits.reset()
cpu.SFlag = Bits.signInTwosComp(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("XOR A")
def xorA(cpu, opcode, logger):
"""XOR A"""
regInd = opcode & 7
cpu.A = cpu.A ^ cpu.regs[regInd]
"""Flags"""
cpu.flags[ZF] = Bits.isZero(cpu.A)
cpu.flags[CF] = False
cpu.flags[NF] = False
cpu.flags[HF] = False
cpu.flags[SF] = Bits.signInTwosComp(cpu.A)
cpu.flags[PVF] = Bits.paritySet(cpu.A)
logger.info("XOR A")
def _and_hl(cpu, opcode, logger):
val = cpu.ram[cpu.HL]
cpu.A = cpu.A & val
cpu.HFlag = Bits.set()
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.signInTwosComp(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 7
logger.info("AND (HL)")
