def rlca(cpu, opcode, logger):
cflag = Bits.getNthBit(cpu.A, 7)
cpu.A = Bits.setNthBit(cpu.A << 1, 0, cflag)
cpu.CFlag = Bits.set() if cflag != 0 else Bits.reset()
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("RLCA")
def rra(cpu, opcode, logger):
cflag = Bits.getNthBit(cpu.A, 0)
cpu.A = Bits.setNthBit((cpu.A >> 1), 7, cpu.CFlag)
cpu.CFlag = Bits.set() if cflag == 1 else Bits.reset()
cpu.HFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("RRA")
def bit_res(cpu, opcode, logger):
index = (opcode >> 8) & 255
bit = (opcode >> 3) & 7
val = cpu.ram[cpu.IY+index]
val = Bits.setNthBit(val, bit, 0)
cpu.ram[cpu.IY+index] = val
cpu.m_cycles, cpu.t_states = 6, 23
logger.info("RES {}, (IY+{:02X})".format(bit, index))
def lra(cpu, opcode, logger):
cflag = Bits.getNthBit(cpu.A, 7)
cpu.A = Bits.setNthBit((cpu.A << 1), 0, cpu.CFlag)
cpu.CFlag = Bits.set() if cflag == 1 else Bits.reset()
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("LRA")
def PVFlag(self, value):
self.F = Bits.setNthBit(self.F, PVF, 1 if value else 0)
def ZFlag(self, value):
self.F = Bits.setNthBit(self.F, ZF, 1 if value else 0)
def test_bits_setNthBit_correctly_set_the_but(self):
self.assertEquals(32, Bits.setNthBit(0, 5, 1))
def XFlag(self, value: bool):
self.F = Bits.setNthBit(self.F, XF, 1 if value else 0)
def PVFlag(self, value):
self.F = Bits.setNthBit(self.F, PVF, 1 if value else 0)
def SFlag(self, value):
self.F = Bits.setNthBit(self.F, SF, 1 if value else 0)
def test_bits_setNthBit_correctly_set_the_but(self):
self.assertEqual(32, Bits.setNthBit(0, 5, 1))