def dec_at_hl(cpu, opcode, logger):
old_val = cpu.ram[cpu.HL]
new_val = old_val - 1
cpu.ram[cpu.HL] = new_val
cpu.ZFlag = Bits.isZero(new_val)
cpu.SFlag = Bits.isNegative(new_val)
cpu.NFlag = Bits.set()
cpu.PVFlag = Bits.halfCarrySub(old_val, new_val)
cpu.m_cycles, cpu.t_states = 3, 11
logger.info("DEC (HL)")
def adc_r(cpu, opcode, logger):
reg_idx = (opcode & 7)
old_val = cpu.A
cpu.A = old_val + cpu.regs[reg_idx] + (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.NFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("ADC A, {}".format(IndexToReg.translate8Bit(reg_idx)))
def dec_at_ix_d(cpu, opcode, logger):
d = cpu.ram[cpu.PC]
old_val = cpu.ram[cpu.IX+d]
new_val = old_val - 1
cpu.ram[cpu.IX+d] = new_val
cpu.ZFlag = Bits.isZero(new_val)
cpu.SFlag = Bits.isNegative(new_val)
cpu.NFlag = Bits.set()
cpu.PVFlag = Bits.halfCarrySub(old_val, new_val)
cpu.m_cycles, cpu.t_states = 6, 23
logger.info("DEC (IX+{:02X})".format(d))
def _or_hl(cpu, opcode, logger):
cpu.A = cpu.A | cpu.ram[cpu.HL]
cpu.HFlag = Bits.reset()
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("OR (HL)")
def neg(cpu, opcode, logger):
old = cpu.A
cpu.A = 0 - cpu.A
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.set() if old == 0x80 else Bits.reset()
cpu.CFlag = Bits.isZero(old)
cpu.HFlag = Bits.halfCarrySub(0x0, old)
cpu.m_cycles, cpu.t_states = 2, 8
logger.info("NEG")
def ldar(cpu, opcode, logger):
cpu.A = cpu.R
cpu.SFlag = Bits.isNegative(cpu.R)
cpu.ZFlag = Bits.isZero(cpu.R)
cpu.HFlag = Bits.reset()
cpu.PVFlag = Bits.set() if cpu.iff2 == 1 else Bits.reset()
cpu.NFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 2, 9
logger.info("LD A, R")
def _or(cpu, opcode, logger):
regInd = opcode & 7
cpu.A = cpu.A | cpu.regs[regInd]
cpu.HFlag = Bits.reset()
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("OR {}".format(IndexToReg.translate8Bit(regInd)))
def inc8(cpu, opcode, logger):
index = (opcode >> 3) & 7
oldValue = cpu.regs[index]
cpu.regs[index] = Bits.limitTo8Bits(cpu.regs[index] + 1)
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.regs[index])
cpu.HFlag = Bits.halfCarrySub(oldValue, cpu.regs[index])
cpu.PVFlag = True if oldValue == 0x7f else False
cpu.SFlag = Bits.isNegative(cpu.regs[index])
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("INC {}".format(IndexToReg.translate8Bit(index)))
def sbc_hl(cpu, opcode, logger):
old_val = cpu.A
cpu.A = old_val - cpu.ram[cpu.HL] - (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.NFlag = Bits.set()
cpu.HFlag = Bits.halfCarrySub(old_val, cpu.A)
cpu.PVFlag = Bits.overflow(old_val, cpu.A)
cpu.CFlag = Bits.carryFlag(cpu.A)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("SDC A, (HL)")
def cp_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
old = cpu.A
new = old - n
cpu.SFlag = Bits.isNegative(new)
cpu.ZFlag = Bits.isZero(new)
cpu.HFlag = Bits.halfCarrySub(old, new)
cpu.PVFlag = Bits.overflow(old, new)
cpu.NFlag = Bits.set()
cpu.CFlag = Bits.carryFlag(new)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("CP {:02X}".format(n))
def dec_mem_at_iy(cpu, opcode, logger):
displacement = cpu.ram[cpu.PC]
addr = cpu.IY + displacement
value = cpu.ram[addr]
new_value = value - 1
cpu.ram[addr] = new_value
cpu.NFlag = Bits.set()
cpu.SFlag = Bits.isNegative(new_value)
cpu.ZFlag = Bits.isZero(new_value)
cpu.PVFlag = True if value == 0x80 else False
cpu.HFlag = Bits.halfCarrySub(value, new_value)
logger.info("DEC (IY+{:2X})".format(displacement))
def dec8b(cpu, opcode, logger):
reg_index = (opcode >> 3) & 7
old_val = cpu.regs[reg_index]
cpu.regs[reg_index] = cpu.regs[reg_index] - 1
cpu.ZFlag = Bits.isZero(cpu.regs[reg_index])
cpu.SFlag = Bits.isNegative(cpu.regs[reg_index])
cpu.NFlag = Bits.set()
cpu.PVFlag = Bits.halfCarrySub(old_val, cpu.regs[reg_index])
cpu.HFlag = Bits.halfCarrySub(old_val, cpu.regs[reg_index])
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("DEC {}".format(IndexToReg.translate8Bit(reg_index)))
def sbc_r(cpu, opcode, logger):
reg_idx = (opcode & 7)
old_val = cpu.A
cpu.A = old_val - cpu.regs[reg_idx] - (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.NFlag = Bits.set()
cpu.HFlag = Bits.halfCarrySub(old_val, cpu.A)
cpu.PVFlag = Bits.overflow(old_val, cpu.A)
cpu.CFlag = Bits.carryFlag(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("SDC A, {}".format(IndexToReg.translate8Bit(reg_idx)))
def sub_a_hl(cpu, opcode, logger):
v = cpu.ram[cpu.HL]
old_A = cpu.AFPrim
cpu.A -= v
cpu.NFlag = Bits.set()
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.HFlag = Bits.halfCarrySub(old_A, cpu.A)
cpu.PVFlag = Bits.overflow(old_A, cpu.A)
cpu.CFlag = Bits.carryFlag(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 7
logger.info("SUB A, (HL)")
def adc_a_hl(cpu, opcode, logger):
v = cpu.ram[cpu.HL]
old = cpu.A
cpu.A += v
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.NFlag = Bits.reset()
cpu.PVFlag = Bits.overflow(old, cpu.A)
cpu.HFlag = Bits.halfCarrySub(cpu.A, old)
cpu.CFlag = Bits.carryFlag(old + v)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("ADC A, (HL)")
def xor_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
old = cpu.A
cpu.A = old ^ n
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.HFlag = Bits.reset()
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("XOR {:02X}".format(n))
def add_a_hl(cpu, opcode, logger):
oldA = cpu.A
value = cpu.A + cpu.ram[cpu.HL]
cpu.A = value
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.carryFlag(value)
cpu.PVFlag = Bits.overflow(oldA, cpu.A)
cpu.HFlag = Bits.halfCarrySub(cpu.A, oldA)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("ADD A, (HL)")
def adc_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
old_val = cpu.A
new_val = cpu.A + n + (1 if cpu.CFlag else 0)
cpu.A = new_val
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.HFlag = Bits.halfCarrySub(old_val, cpu.A)
cpu.PVFlag = Bits.overflow(old_val, cpu.A)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.carryFlag(new_val)
logger.info("ADC A, {:02X}".format(n))
def add_r(cpu, opcode, logger):
index = (opcode & 7)
old = cpu.A
cpu.A = old + cpu.regs[index]
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.HFlag = Bits.halfCarrySub(old, cpu.A)
cpu.PVFlag = Bits.overflow(old, cpu.A)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.carryFlag(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("ADD A, {}".format(IndexToReg.translate8Bit(index)))
def or_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
old = cpu.A
cpu.A = cpu.A | n
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.HFlag = Bits.reset()
cpu.PVFlag = Bits.overflow(old, cpu.A)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("OR {:02X}".format(n))
def add_iy(cpu, opcode, logger):
d = cpu.ram[cpu.PC]
value = cpu.A + cpu.ram[cpu.IY+d]
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.CFlag = Bits.carryFlag(value)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.overflow(cpu.A, value)
cpu.HFlag = Bits.halfCarrySub(cpu.A, value)
cpu.A = value
cpu.m_cycles, cpu.t_states = 4, 15
logger.info("ADD A, (IY+{:02X})".format(d))
def rrd(cpu, opcode, logger):
low_a = cpu.A & 0x0F
mem_hl = cpu.ram[cpu.HL]
low_hl = mem_hl & 0x0F
high_hl = (mem_hl & 0xF0) >> 4
cpu.A = (cpu.A & 0xF0) | low_hl
mem_hl = (low_a << 4) | high_hl
cpu.ram[cpu.HL] = mem_hl
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.HFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 5, 18
logger.info("RRD")
def sub_r(cpu, opcode, logger):
index = opcode & 7
old_A = cpu.A
cpu.A = cpu.A - cpu.regs[index]
cpu.NFlag = Bits.set()
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.HFlag = Bits.halfCarrySub(old_A, cpu.A)
cpu.PVFlag = Bits.overflow(cpu.A, old_A)
cpu.CFlag = Bits.carryFlag(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("SUB {}".format(IndexToReg.translate8Bit(index)))
def add_r_n(cpu, opcode, logger):
n = cpu.ram[cpu.PC]
old = cpu.A
value = cpu.A + n
cpu.A = value
cpu.SFlag = Bits.isNegative(value)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.HFlag = Bits.halfCarrySub(old, cpu.A)
cpu.PVFlag = Bits.overflow(old, cpu.A)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.carryFlag(value)
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("ADD A, {:02X}".format(n))
def test_bits_isNegative_returns_true_if_value_is_over_80h(self):
self.assertTrue(Bits.isNegative(0x81))
def test_bits_isNegative_returns_true_for_16bit_if_value_is_over_8000h(self):
self.assertTrue(Bits.isNegative(0x8000, bits=16))
def test_bits_isNegative_returns_false_for_16bit_if_value_is_below_8000h(self):
self.assertFalse(Bits.isNegative(0x2000, bits=16))
def test_bits_isNegative_returns_true_if_value_is_over_80h(self):
self.assertTrue(Bits.isNegative(0x81))
def test_bits_isNegative_returns_false_if_value_is_below_80h(self):
self.assertFalse(Bits.isNegative(0x20))
def test_bits_isNegative_returns_true_for_16bit_if_value_is_over_8000h(self):
self.assertTrue(Bits.isNegative(0x8000, bits=16))
def test_bits_isNegative_returns_false_for_16bit_if_value_is_below_8000h(self):
self.assertFalse(Bits.isNegative(0x2000, bits=16))
def test_bits_isNegative_returns_false_if_value_is_below_80h(self):
self.assertFalse(Bits.isNegative(0x20))
